I am busy developing program containing both local eCAP and IEP timers. The main loop is becoming relative 'slow' because of the need of polling both timer timeouts.
I am trying to replace the tedious polling instructions and to use R31 bits 30 and 31 as PRU interrupt 0 and 1 from IEP and eCAP, but so far without success.I try to use interrupt 7 (pr1_iep_tim_cap_cmp_pend) and interrupt 15 (pr1_ecap_intr_req).
I have followed the steps as mentioned in PRU Interrupt Controller wiki and PRUSSV2 handling
Note that the first document is not intended for the AM335x.
Question 1:
Has anybody a PRUSSV2 interrupt example for me to check what i do wrong or have missed?
Question 2::
The description of the HIEISR register (AM335x PRU-ICSS Reference Guide chapter 6.4.9) is a bit unclear for me:
The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt
to enable is the index value written. This enables the host interrupt output or triggers the output again if
already enabled.
Does that mean that if I want to enable host interrupts 0 and 1, that I have to perform two write actions; 0x00, followed by 0x01?
Part of my code is listed below:
// Disable MII_RT (EthercaT) Events to the INTC
LBCO r0, PRU_CTAB_PRUSS_CFG, CFG_MII_RT, 4
CLR r0, r0, 0 // Use external events (not ethercat events)
SBCO r0, PRU_CTAB_PRUSS_CFG, CFG_MII_RT, 4
//
// route pr1_iep_tim_cap_cmp_pend (int number 7) to PRU interrupt 1 (R31 bit 31)
// route pr1_ecap_intr_req (int number 15) to PRU interrupt 0 (R31 bit 30)
//
// Clear global interrupt
LBCO r0, PRU_CTAB_LOC_INTC, INTC_GER, 4
clr r0, r0, 0
SBCO r0, PRU_CTAB_LOC_INTC, INTC_GER, 4
// Follow these steps to configure the interrupt controller.
// 1. Set polarity and type of system event through the System Interrupt Polarity Registers (SIPR1 and
// SPIR2) and the System Interrupt Type Registers (SITR1 and SITR2). Polarity of all system interrupts is
// always high. Type of all system interrupts is always pulse.
// active high, level interrupt
mov r1, INTC_SIPR0
LBCO r0, PRU_CTAB_LOC_INTC, r1, 4
set r0, r0, 7 // IEP cmp status active high
set r0, r0, 15 // eCAP interrupt status active high
SBCO r0, PRU_CTAB_LOC_INTC, r1, 4
mov r1, INTC_SITR0
LBCO r0, PRU_CTAB_LOC_INTC, r1, 4
clr r0, r0, 7
clr r0, r0, 15
SBCO r0, PRU_CTAB_LOC_INTC, r1, 4
// 2. Map system event to INTC channel through CHANMAP registers.
// Map system interrupt 7 to channel 0
mov r1, INTC_CMR1
LBCO r0, PRU_CTAB_LOC_INTC, r1, 4
M_MOV32 r2, 0xF0FFFFFF
and r0, r0, r2
SBCO r0, PRU_CTAB_LOC_INTC, r1, 4
// Map system interrupt 15 to channel 1
mov r1, INTC_CMR3
LBCO r0, PRU_CTAB_LOC_INTC, r1, 4
M_MOV32 r2, 0xF0FFFFFF
and r0, r0, r2
M_MOV32 r2, 0x01000000
or r0, r0, r2
SBCO r0, PRU_CTAB_LOC_INTC, r1, 4
// 3. Map channel to host interrupt through HOSTMAP registers. Recommend channel “x” be mapped to
// host interrupt “x”.
// Map channel 0 to host interrupt 0, 1 to 1, ...
mov r1, INTC_HMR0
M_MOV32 r0, 0x03020100
SBCO r0, PRU_CTAB_LOC_INTC, r1, 4
mov r1, INTC_HMR1
M_MOV32 r0, 0x07060504
SBCO r0, PRU_CTAB_LOC_INTC, r1, 4
mov r1, INTC_HMR2
M_MOV32 r0, 0x00000908
SBCO r0, PRU_CTAB_LOC_INTC, r1, 4
// 4. Clear system interrupt by writing 1s to SECR registers.
M_MOV32 r0, 0xFFFFFFFF
mov r1, INTC_SECR0
SBCO r0, PRU_CTAB_LOC_INTC, r1, 4
mov r1, INTC_SECR1
SBCO r0, PRU_CTAB_LOC_INTC, r1, 4
// 5. Enable host interrupt by writing index value to HOSTINTENIDX register.
mov r1, INTC_HIEISR
M_MOV32 r0, 0x01 // enable host interrupt 01
SBCO r0, PRU_CTAB_LOC_INTC, r1, 4
M_MOV32 r0, 0x00 // enable host interrupt 00
SBCO r0, PRU_CTAB_LOC_INTC, r1, 4
// 6. Enable interrupt nesting if desired.
LBCO r0, PRU_CTAB_LOC_INTC, INTC_CR, 4
clr r0, r0, 2
clr r0, r0, 3
SBCO r0, PRU_CTAB_LOC_INTC, INTC_CR, 4
// 7. Globally enable all interrupts through GLBLEN register.
LBCO r0, PRU_CTAB_LOC_INTC, INTC_GER, 4
set r0, r0, 0
SBCO r0, PRU_CTAB_LOC_INTC, INTC_GER, 4
The eCAP interrupt is enabled via:
// Set Counter Equal Period Interrupt Enable
mov r2, 0x40
sbco r2, PRU_CTAB_ECAP, ECAP_OFFS_ECEINT, 2 // Counter Equal Period Interrupt Enable
As far as I can see is there no interrupt enable bit present in the IEP.
In 10.2.2.1 is stated:
– One global event output for interrupt generation triggered by any compare event.