Hi,
I have tried to use the Clock Tree Tool to visualize all the clock domains.
When I try to configure the Peripheral PLL (DPLL_PER in the tool) I do not get the 192MHz out of the PLL with the values we use in our design:
N=23
M=960
M2=5
This should result in:
CLKDCOLDO=960MHz
CLKOUT M2=192MHz
Because the AM3359 GEL File also uses this parameters I think there is a problem in the tool.
Do I miss a parameter in the tool?
Thanks.
Best regards,
Patrick