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AM335x and phy KSZ9031

Thiago Marques
Prodigy 90 points

I have a question. Someone already use the am335x and KSZ9031?
I have a custom board, this board is based in Starter Kit and KSZ9031RNX Evaluation Board.
And in my case the status of the LED1 toggle and LED2 your state is high, have signals in pin RX, but TX enable and pin TX are in down. The kernel recognizes the phy:

[ 65.114071] net eth0: CPSW phy found : id is : 0x7c0f1

But I when do ifconfig, don't have RX or TX, 0 bytes

root@am335x-evm:~# ifconfig
eth0 Link encap:Ethernet HWaddr BC:6A:29:99:F3:58
inet addr:192.168.1.221 Bcast:192.168.1.255 Mask:255.255.255.0
UP BROADCAST MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)

what can be?

thanks

  • 0
    TI__Mastermind 27720 points

    Thiago,

    You may want to search this forum for other customers using this PHY...I do believe we have more than one doing so.

    Have you verified via the PHY configuration registers that the PHY is correctly configured and that the configuration matches that of the MAC? Dump the PHY registers and compare them against the MAC's MACCONTROL register to be sure. GMII_SEL should also be checked to ensure you have the port(s) in the correct mode.

    Did you perform a timing analysis of the RGMII interface prior to comitting the design to PCB? The timing on this interface is VERY tight...

  • 0 in reply to -DK-
    Prodigy 90 points

    thanks DK,

    I will view  a timing analysis of the RGMII interface, because  the RX data to RX clock output characteristics of the KSZ9031 is +/-500ps and the AM335x input requires a minimum 1ns 

  • 0 in reply to Thiago Marques
    Prodigy 90 points

    When my kernel starts , it prints:

    davinci_mdio davinci_mdio.0: phy[0]: device 0:00, driver Micrel KSZ9031 Gigabit PHY
    davinci_mdio davinci_mdio.0: phy[3]: device 0:03, driver Micrel KSZ9031 Gigabit PHY

    So in my kernel source I changed

    am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, NULL, NULL);

    to

    am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, "0:00", "0:03");

    So the pin TX enable is in up. And the phy works.