This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335x NAND flash 2k pages 128 bytes spare area

Expert 1915 points

Hello,

The TRM (i) shos that the AM335x support booting from a 2k + 64 NAND:

Support for large page size (2048 bytes + 64 spare bytes) or very large page size 4096 bytes + 128 /
218 spare bytes)

Can it also boot  form a NAND device that has 2k pages and 128 spare bytes?

Will I need to write the ECC bits with a stride or at the beginning (after bb marker)?

Will the ROM code expect BCH8?

This is the NAND: <http://www.spansion.com/Support/Datasheets/S34ML01G2_04G2.pdf>

(S34ML04G2 in x8)

Regards,

Lo2

  • Hi Lo2,
     
    Yes, this NAND device is listed as supported by the AM335X ROM code (AM335X TRM, Rev.I, Table 26-14). For the other questions please check this link: http://processors.wiki.ti.com/index.php/AM335x_U-Boot_User's_Guide#NAND_2
  • Hello Biser,

    thanks for your fast reply!

    Will the rom code expect BCH8 ECC in the spare area?

    Regards,

    Lo2

  • This will depend on SYSBOOT[9] value at boot time. See AM335X TRM Rev.I page 4695 "ECC Correction" for details.
  • I selected SYSBOOT[9]=1 -> ECC by ROM since the NAND has no internal ECC.

    But how many spare bits for the ECC algortihm does the ROM code expect?

    Accirding to 26.1.7.4.1:

    " ECC correction : 8 bits/sector for most devices (16b/sector for devices with large spare area)"

    basically: is 128bytes a large spare area?

    I flashed my NAND, when I disable ECC (sysboot[9]=0) it boots. When I enable ECC (sysboot[9]=1) the it won't boot. So I assume something goes wrong with the ECC checksum.

    Regards,

    Lo2

  •  SYSBOOT[9]=1 is ECC handled by NAND, SYSBOOT[9]=0 is ECC done by ROM code  (Table 26-7 in the AM335X TRM, Rev.I). 
  • Hello Biser,

    My sysboot 9 setting is ok, I want it to boot from NAND with ECC. Without ECC is ok for testing but no option for a production system.

    Meanwhile I got the AM335x to boot from a Spansion S34ML04G2 NAND flash with 2k pages and 128 spare bytes.

    The default MLO/u-boot won't work (with ECC) because it will always use BCH8 ECC but the ROM code expects BCH16 ECC for the Spansion flash.

    To program the flash I modified my MLO & u-boot now I can write the flash with BCH16 ECC.

    I just wonder if the Micron flash with 2k pages & 128 spare bytes mentioned on the processor wiki was tested with or without ECC. And if ECC was used, which algorithm was used?

    Anyway it would be good if there was a clearer description which algorithm the ROM code expects when booting from NAND flash with ECC enabled.

    Regards,

    Lo2

  • Hi Lo2,
     
    The TRM section mentioned above (AM335X TRM Rev.I page 4695 "ECC Correction") does mention this:
     
    "The default ECC correction applied is BCH 8b/sector using the GPMC and ELM hardware.
     
    For device ID codes D3h, C3h, D5h, C5h, D7h, C7h, DEh, CEh when manufacturer code (first ID byte) is 98h the Cell type information is checked in the 4th byte of ID data. If it is equal to 10b then the ECC correction applied is BCH 16b/sector.
     
    In addition ECC computation done by the ROM can be turned off completely by using SYSBOOT[9]. This is particularly useful when interfacing with NAND devices that have built in ECC engines."
     
    I agree that the list of BCH16 devices may not be comprehensive.

  • Dear Sir,

              I am using S34ML01G100BH Spansion 8 bit Nand Flash,  Man. ID = 0x01 and Devide ID=0x1F. This par is not in the list, so why should I aplly BCH 16b/sector?

    Best Regards.

    Francisco.