beaglebone A5 ddr2 config

The image is missing from your post. Can you please resend?

http://www.ti.com/lit/ug/spruh73j/spruh73j.pdf

page 595

And sorry it should be 0x418052B2 

Thanks Biser

Another question 

From  comment of 28-27 reg_ibank_pos

Set to 0 to assign internal bank address bits from lower OCP
address bits, as shown in the tables for OCP Address to
DDR2/3/mDDR Address Mapping.
Set to 1, 2, or 3 to assign internal bank address bits from higher
OCP address, as shown in the tables for OCP Address to
DDR2/3/mDDR Address Mapping.
26-24 reg_ddr_term R/W 0h DDR2 and DDR3 termination resistor

How do OCP know the raw size from different ddr chips ? 

Regards 

See section 7.3.3.4 in the AM335X TRM Rev. J.

Thanks again 

And seems in this case we use from 

7.3.3.4.1 Address Mapping when REG_IBANK_POS=0 and REG_EBANK_POS=0

but , what I still confuse is how does the EMIF translate the address ?

For example , assume we still use the same ddr2 chip , we access 0x2000004, this mean use the bank 1 column 0 and raw 0, but ,how does EMIF know its not bank 0 column 0 and raw 16k+1 ?

Sorry bother you again ,but the document doesn't say more detail about this, 

Thanks and regards 

Or , does this mean address translate 

First column address , second bank address ,then raw address ?