AM335X spi rx1_full irq?

Hi,

Please check Chapter 10 of Linux Device Drivers 3rd: Interrupt Handling: http://lwn.net/Kernel/LDD3/

Best regards,
Miroslav

I know linux interrupt handle, but I don't not know SPI rx1_full irq number. 

I want to know SPI rx1_full irq number.

Thanks!

Check Table 6.1 ARM Cortex-A8 Interrupts from the AM335x TRM (chapter 6.3). McSPI0 uses INT number 65 and McSPI1 uses INT number 125. You then need to check the MCSPI_IRQSTATUS register in your interrupt handler to determine what caused the interrupt.

Best regards,
Miroslav

Thank Miroslav Kiradzhiyski.

I have use McSPI1 int nimber 125, but it can not input interrupt ISR, need other setting?

    status = request_irq(125, spi_rx_full_isr, 0, "spi_rx_full_irq", mcspi);

    // Enable IRQ on RX1 full
    irq_enable = 0x00000000;
    MOD_REG_BIT(irq_enable, OMAP2_MCSPI_IRQ_RX1_FULL_ENABLE, 1);
    mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, irq_enable);            

A similar situation.

if (request_irq(125, spi_handler, IRQF_SHARED, "spi1", &control[1])) {
			printk(KERN_ALERT "fail reuest interrupt for spi1\n");
			status = -EIO;
			goto stop_edma_spi1;
		}

Handler never called

Maybe need other setting?

After the function request_irq I watch register INTC_MIR3. Value INTC_MIR3  = FFFFDFFA. 125 is a bit 20000000.Thus interrupt number 125 still masked.After setting the flag RX1_FULL, I see the value of register INTC_ITR3.Value INTC_ITR3  = 20000000. Interrupt is set. But it is not processed because masked (value INTC_MIR3  = FFFFDFFA). This demonstrates that the interrupt system is not working properly.
THIS IS TERRIBLE!!!

Dear korobchenko andrej korobchenko andrej,

    do you have a good solution? thanks!

I am also in same situation. do you have any solution for it?