This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Dear, the arm in my custom board is AM3359, and the phy chip is ar8035, the interface between the am3359 mac and the phy CHIP is RGMII1, can I use the am335x ndk cpsw driver (form am335x_sysbios_ind_sdk_1.1.0.4)in my custom board directly? Or anything do I need to do?
The software environment : am335x_sysbios_ind_sdk_1.1.0.4, bios_6_35_04_50,ndk_2_22_03_20,xdctools_3_25_03_72,ccs v5.5
Best regards,
Rolan
Rolan,
The implementation in SDK 1.1.0.4 is supported only for ICE/IDK boards. To make it run on custom boards, you will have to modify the pinmux, Phy addresses, Phy registers(if there is a different in the standard PHY registers).
Regards,
Vinesh
Vinesh,
I have tried to modify the pinmux,Phy addresses, and funtions "static void cpgmacMacOpen(Cpsw3gPort *hPort)",
"static void cpsw3g_SetMacCfg(Cpsw3gPort* hPort)" in fle "cpsw_impl.c", but the packets coouldn't be sent out, would you mind telling me specifically which functions should be modified ?
Regards,
Rolan
Rolan,
Please share more details on what issue is being seen.
The pinmux changes should be done the structure which is passed into PinMuxConfig, The Phy addresses can be configured using SetMacConfiguration.
Depending on the hardware changes, RGMII initialization will vary, which will have to be modified in RMIIClock_setup
Regards,
Vinesh
Vinesh,
I modified the "main()" as follow:
Int main()
{
Task_Handle netapp_task;
Error_Block eb;
MAC_CONFIG config;
MMUInit(applMmuEntries); //init and enable mmu, cache
// System_atexit(app_exit_handler);
System_printf("enter main()\n");
//init network
//board_Type = UTILsGetBoardType();
#ifdef DEBUG_LINK_STATUS
cpsw_register_link_change_notification(DisplayLinkStatus);
#endif
PinMuxConfig();
CPSWClkEnable();
// LEDInit();
config.phyAddr[0] = 0; //phy address
config.numberPorts = 1;
config.macModeFlags = CPSW_CONFIG_MODEFLG_GIGABIT | CPSW_CONFIG_MODEFLG_FULLDUPLEX;
config.resvd = 1;
SetMacConfiguration(&config);
// uartInstance =0;
//SpiFlashInit(1,0);
PortModeSelect_Ind();
//加载网络驱动
if(AddNetifEntryFn(CPSW_NETIF_INIT) == 0)
{
BIOS_exit(0);
}
/*
* Setting Task_sleep as the delay function for i2c enables i2c APIs to sleep
* in between i2c operations ( instead of going to a tight loop ).
* Here, while in CPSW mode on ICE V2, RMII clock is fed from a clock synthesizer
* which is configured over i2c. This configuration fails if the delay function is not set.
* Note that, from main, no i2c APIs shall be called after this call.
*/
//I2CSetDelayFn(Task_sleep);
Error_init(&eb);
Task_Params taskParams;
Task_Params_init(&taskParams);
taskParams.priority = 3;
taskParams.stackSize = 5120; //tcp at least 4096
netapp_task = Task_create (taskNetAppFxn, &taskParams, &eb);
if (netapp_task == NULL) {
System_printf("Task_create() failed!\n");
BIOS_exit(0);
}
//end of init network
//UartOpen(uartInstance, UartIsr);
UartOpen(uartInstance, NULL);
UARTPutString(uartInstance,"BEGIN");
BIOS_start(); /* does not return */
return(0);
}
and I modified the PinMuxConfig() as follow:
void PinMuxConfig(void)
{
MUX_EVM()
return;
}
MUC_EVM() is defined as follow:
#ifndef _PINMUX_H_
#define _PINMUX_H_
/*
* MODE0 - Mux Mode 0
* MODE1 - Mux Mode 1
* MODE2 - Mux Mode 2
* MODE3 - Mux Mode 3
* MODE4 - Mux Mode 4
* MODE5 - Mux Mode 5
* MODE6 - Mux Mode 6
* MODE7 - Mux Mode 7
* IDIS - Receiver disabled
* IEN - Receiver enabled
* PD - Internal pull-down
* PU - Internal pull-up
* OFF - Internal pull disabled
*/
#define MUX_EVM() \
MUX_VAL(CONTROL_PADCONF_GPMC_AD0, (IEN | PD | MODE0 )) /* GPMC_AD0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD1, (IEN | PD | MODE0 )) /* GPMC_AD1 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD2, (IEN | PD | MODE0 )) /* GPMC_AD2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD3, (IEN | PD | MODE0 )) /* GPMC_AD3 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD4, (IEN | PD | MODE0 )) /* GPMC_AD4 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD5, (IEN | PD | MODE0 )) /* GPMC_AD5 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD6, (IEN | PD | MODE0 )) /* GPMC_AD6 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD7, (IEN | PD | MODE0 )) /* GPMC_AD7 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD8, (IEN | PD | MODE0 )) /* GPMC_AD8 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD9, (IEN | PD | MODE0 )) /* GPMC_AD9 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD10, (IEN | PD | MODE0 )) /* GPMC_AD10 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD11, (IEN | PD | MODE0 )) /* GPMC_AD11 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD12, (IEN | PD | MODE0 )) /* GPMC_AD12 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD13, (IEN | PD | MODE0 )) /* GPMC_AD13 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD14, (IEN | PD | MODE0 )) /* GPMC_AD14 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD15, (IEN | PD | MODE0 )) /* GPMC_AD15 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A0, (IDIS | PD | MODE0 )) /* GPMC_A0_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IDIS | PD | MODE0 )) /* GPMC_A1_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IDIS | PD | MODE0 )) /* GPMC_A2_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IDIS | PD | MODE0 )) /* GPMC_A3_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IDIS | PD | MODE0 )) /* GPMC_A4_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IDIS | PD | MODE0 )) /* GPMC_A5_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IDIS | PD | MODE0 )) /* GPMC_A6_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IDIS | PD | MODE0 )) /* GPMC_A7_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IDIS | PD | MODE0 )) /* GPMC_A8_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IDIS | PD | MODE0 )) /* GPMC_A9_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IDIS | PD | MODE0 )) /* GPMC_A10_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IDIS | PD | MODE0 )) /* GPMC_A11_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | PU | MODE7 )) /* GPIO0[30] */\
MUX_VAL(CONTROL_PADCONF_GPMC_WPN, (IEN | PU | MODE7 )) /* GPIO0[31] */\
MUX_VAL(CONTROL_PADCONF_GPMC_BEN1, (IEN | PU | MODE7 )) /* GPIO1[28] */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN0, (IDIS | PU | MODE0 )) /* GPMC_CSN0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN1, (IDIS | PU | MODE0 )) /* GPMC_CSN1 */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN2, (IEN | PU | MODE7 )) /* GPIO1[31] */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN3, (IEN | PU | MODE7 )) /* GPIO2[0] */\
MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | PD | MODE0 )) /* GPMC_CLK_MUX0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_ADVN_ALE, (IEN | PU | MODE7 )) /* GPIO2[2] */\
MUX_VAL(CONTROL_PADCONF_GPMC_OEN_REN, (IDIS | PU | MODE0 )) /* GPMC_OEN_REN */\
MUX_VAL(CONTROL_PADCONF_GPMC_WEN, (IDIS | PU | MODE0 )) /* GPMC_WEN */\
MUX_VAL(CONTROL_PADCONF_GPMC_BEN0_CLE, (IEN | PU | MODE7 )) /* GPIO2[5] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA0, (IEN | OFF | MODE7 )) /* GPIO2[6] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA1, (IEN | OFF | MODE7 )) /* GPIO2[7] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA2, (IEN | OFF | MODE7 )) /* GPIO2[8] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA3, (IEN | OFF | MODE7 )) /* GPIO2[9] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA4, (IEN | OFF | MODE7 )) /* GPIO2[10] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA5, (IEN | OFF | MODE7 )) /* GPIO2[11] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA6, (IEN | OFF | MODE7 )) /* GPIO2[12] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA7, (IEN | OFF | MODE7 )) /* GPIO2[13] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA8, (IEN | OFF | MODE7 )) /* GPIO2[14] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA9, (IEN | OFF | MODE7 )) /* GPIO2[15] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA10, (IEN | OFF | MODE7 )) /* GPIO2[16] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA11, (IEN | OFF | MODE7 )) /* GPIO2[17] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA12, (IEN | OFF | MODE7 )) /* GPIO0[8] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA13, (IEN | OFF | MODE7 )) /* GPIO0[9] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA14, (IEN | OFF | MODE7 )) /* GPIO0[10] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA15, (IEN | OFF | MODE7 )) /* GPIO0[11] */\
MUX_VAL(CONTROL_PADCONF_LCD_VSYNC, (IEN | OFF | MODE7 )) /* GPIO2[22] */\
MUX_VAL(CONTROL_PADCONF_LCD_HSYNC, (IEN | OFF | MODE7 )) /* GPIO2[23] */\
MUX_VAL(CONTROL_PADCONF_LCD_PCLK, (IEN | OFF | MODE7 )) /* GPIO2[24] */\
MUX_VAL(CONTROL_PADCONF_LCD_AC_BIAS_EN, (IEN | OFF | MODE7 )) /* GPIO2[25] */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT3, (IEN | PU | MODE7 )) /* GPIO2[26] */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT2, (IEN | PU | MODE7 )) /* GPIO2[27] */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT1, (IEN | PU | MODE3 )) /* UART3_RXD_MUX2 */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT0, (IDIS | PU | MODE3 )) /* UART3_TXD_MUX2 */\
MUX_VAL(CONTROL_PADCONF_MMC0_CLK, (IEN | PU | MODE3 )) /* UART2_RXD_MUX2 */\
MUX_VAL(CONTROL_PADCONF_MMC0_CMD, (IDIS | PU | MODE3 )) /* UART2_TXD_MUX2 */\
MUX_VAL(CONTROL_PADCONF_MII1_COL, (IEN | PD | MODE7 )) /* GPIO3[0] */\
MUX_VAL(CONTROL_PADCONF_MII1_CRS, (IEN | PD | MODE3 )) /* I2C1_SDA_MUX0 */\
MUX_VAL(CONTROL_PADCONF_MII1_RX_ER, (IEN | PD | MODE3 )) /* I2C1_SCL_MUX0 */\
MUX_VAL(CONTROL_PADCONF_MII1_TX_EN, (IDIS | PD | MODE2 )) /* RGMII1_TCTL */\
MUX_VAL(CONTROL_PADCONF_MII1_RX_DV, (IEN | PD | MODE2 )) /* RGMII1_RCTL */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD3, (IDIS | PD | MODE2 )) /* RGMII1_TD3 */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD2, (IDIS | PD | MODE2 )) /* RGMII1_TD2 */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD1, (IDIS | PD | MODE2 )) /* RGMII1_TD1 */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD0, (IDIS | PD | MODE2 )) /* RGMII1_TD0 */\
MUX_VAL(CONTROL_PADCONF_MII1_TX_CLK, (IDIS | PD | MODE2 )) /* RGMII1_TCLK */\
MUX_VAL(CONTROL_PADCONF_MII1_RX_CLK, (IEN | PD | MODE2 )) /* RGMII1_RCLK */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD3, (IEN | PD | MODE2 )) /* RGMII1_RD3 */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD2, (IEN | PD | MODE2 )) /* RGMII1_RD2 */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD1, (IEN | PD | MODE2 )) /* RGMII1_RD1 */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD0, (IEN | PD | MODE2 )) /* RGMII1_RD0 */\
MUX_VAL(CONTROL_PADCONF_RMII1_REF_CLK, (IEN | PD | MODE7 )) /* GPIO0[29] */\
MUX_VAL(CONTROL_PADCONF_MDIO, (IEN | PU | MODE0 )) /* MDIO_DATA */\
MUX_VAL(CONTROL_PADCONF_MDC, (IDIS | PU | MODE0 )) /* MDIO_CLK */\
MUX_VAL(CONTROL_PADCONF_SPI0_SCLK, (IEN | OFF | MODE0 )) /* SPI0_SCLK */\
MUX_VAL(CONTROL_PADCONF_SPI0_D0, (IEN | OFF | MODE0 )) /* SPI0_D0 */\
MUX_VAL(CONTROL_PADCONF_SPI0_D1, (IEN | OFF | MODE0 )) /* SPI0_D1 */\
MUX_VAL(CONTROL_PADCONF_SPI0_CS0, (IEN | OFF | MODE0 )) /* SPI0_CS0 */\
MUX_VAL(CONTROL_PADCONF_SPI0_CS1, (IEN | OFF | MODE7 )) /* GPIO0[6] */\
MUX_VAL(CONTROL_PADCONF_ECAP0_IN_PWM0_OUT, (IEN | OFF | MODE7 )) /* GPIO0[7] */\
MUX_VAL(CONTROL_PADCONF_UART0_CTSN, (IEN | OFF | MODE7 )) /* GPIO1[8] */\
MUX_VAL(CONTROL_PADCONF_UART0_RTSN, (IEN | OFF | MODE7 )) /* GPIO1[9] */\
MUX_VAL(CONTROL_PADCONF_UART0_RXD, (IEN | OFF | MODE0 )) /* UART0_RXD */\
MUX_VAL(CONTROL_PADCONF_UART0_TXD, (IDIS | OFF | MODE0 )) /* UART0_TXD */\
MUX_VAL(CONTROL_PADCONF_UART1_CTSN, (IEN | OFF | MODE0 )) /* UART1_CTSN */\
MUX_VAL(CONTROL_PADCONF_UART1_RTSN, (IDIS | OFF | MODE0 )) /* UART1_RTSN */\
MUX_VAL(CONTROL_PADCONF_UART1_RXD, (IEN | OFF | MODE0 )) /* UART1_RXD */\
MUX_VAL(CONTROL_PADCONF_UART1_TXD, (IDIS | OFF | MODE0 )) /* UART1_TXD */\
MUX_VAL(CONTROL_PADCONF_I2C0_SDA, (IEN | OFF | MODE0 )) /* I2C0_SDA */\
MUX_VAL(CONTROL_PADCONF_I2C0_SCL, (IEN | OFF | MODE0 )) /* I2C0_SCL */\
MUX_VAL(CONTROL_PADCONF_MCASP0_ACLKX, (IDIS | PU | MODE3 )) /* SPI1_SCLK_MUX2 */\
MUX_VAL(CONTROL_PADCONF_MCASP0_FSX, (IEN | PD | MODE3 )) /* SPI1_D0_MUX2 */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AXR0, (IEN | PD | MODE3 )) /* SPI1_D1_MUX2 */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AHCLKR, (IDIS | PU | MODE3 )) /* SPI1_CS0_MUX4 */\
MUX_VAL(CONTROL_PADCONF_MCASP0_ACLKR, (IDIS | PU | MODE7 )) /* GPIO3[18] */\
MUX_VAL(CONTROL_PADCONF_MCASP0_FSR, (IDIS | PU | MODE7 )) /* GPIO3[19] */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AXR1, (IDIS | PU | MODE7 )) /* GPIO3[20] */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AHCLKX, (IEN | PD | MODE0 )) /* MCASP0_AHCLKX_MUX0 */\
MUX_VAL(CONTROL_PADCONF_XDMA_EVENT_INTR0, (IEN | OFF | MODE0 )) /* XDMA_EVENT_INTR0 */\
MUX_VAL(CONTROL_PADCONF_XDMA_EVENT_INTR1, (IEN | OFF | MODE0 )) /* XDMA_EVENT_INTR1 */
#endif
and the MUX_VAL IS DEIFNED AS FOLLOW:
#ifndef _MUX_H_
#define _MUX_H_
/*
* MODE0 - Mux Mode 0
* MODE1 - Mux Mode 1
* MODE2 - Mux Mode 2
* MODE3 - Mux Mode 3
* MODE4 - Mux Mode 4
* MODE5 - Mux Mode 5
* MODE6 - Mux Mode 6
* MODE7 - Mux Mode 7
* IDIS - Receiver disabled
* IEN - Receiver enabled
* PD - Internal pull-down
* PU - Internal pull-up
* OFF - Internal pull disabled
*/
#define MODE0 0
#define MODE1 1
#define MODE2 2
#define MODE3 3
#define MODE4 4
#define MODE5 5
#define MODE6 6
#define MODE7 7
#define IDIS (0 << 5)
#define IEN (1 << 5)
#define PD (0 << 3)
#define PU (2 << 3)
#define OFF (1 << 3)
/*
* To get the physical address the offset has
* to be added to AM335X_CTRL_BASE
*/
#define CONTROL_PADCONF_GPMC_AD0 0x0800
#define CONTROL_PADCONF_GPMC_AD1 0x0804
#define CONTROL_PADCONF_GPMC_AD2 0x0808
#define CONTROL_PADCONF_GPMC_AD3 0x080C
#define CONTROL_PADCONF_GPMC_AD4 0x0810
#define CONTROL_PADCONF_GPMC_AD5 0x0814
#define CONTROL_PADCONF_GPMC_AD6 0x0818
#define CONTROL_PADCONF_GPMC_AD7 0x081C
#define CONTROL_PADCONF_GPMC_AD8 0x0820
#define CONTROL_PADCONF_GPMC_AD9 0x0824
#define CONTROL_PADCONF_GPMC_AD10 0x0828
#define CONTROL_PADCONF_GPMC_AD11 0x082C
#define CONTROL_PADCONF_GPMC_AD12 0x0830
#define CONTROL_PADCONF_GPMC_AD13 0x0834
#define CONTROL_PADCONF_GPMC_AD14 0x0838
#define CONTROL_PADCONF_GPMC_AD15 0x083C
#define CONTROL_PADCONF_GPMC_A0 0x0840
#define CONTROL_PADCONF_GPMC_A1 0x0844
#define CONTROL_PADCONF_GPMC_A2 0x0848
#define CONTROL_PADCONF_GPMC_A3 0x084C
#define CONTROL_PADCONF_GPMC_A4 0x0850
#define CONTROL_PADCONF_GPMC_A5 0x0854
#define CONTROL_PADCONF_GPMC_A6 0x0858
#define CONTROL_PADCONF_GPMC_A7 0x085C
#define CONTROL_PADCONF_GPMC_A8 0x0860
#define CONTROL_PADCONF_GPMC_A9 0x0864
#define CONTROL_PADCONF_GPMC_A10 0x0868
#define CONTROL_PADCONF_GPMC_A11 0x086C
#define CONTROL_PADCONF_GPMC_WAIT0 0x0870
#define CONTROL_PADCONF_GPMC_WPN 0x0874
#define CONTROL_PADCONF_GPMC_BEN1 0x0878
#define CONTROL_PADCONF_GPMC_CSN0 0x087C
#define CONTROL_PADCONF_GPMC_CSN1 0x0880
#define CONTROL_PADCONF_GPMC_CSN2 0x0884
#define CONTROL_PADCONF_GPMC_CSN3 0x0888
#define CONTROL_PADCONF_GPMC_CLK 0x088C
#define CONTROL_PADCONF_GPMC_ADVN_ALE 0x0890
#define CONTROL_PADCONF_GPMC_OEN_REN 0x0894
#define CONTROL_PADCONF_GPMC_WEN 0x0898
#define CONTROL_PADCONF_GPMC_BEN0_CLE 0x089C
#define CONTROL_PADCONF_LCD_DATA0 0x08A0
#define CONTROL_PADCONF_LCD_DATA1 0x08A4
#define CONTROL_PADCONF_LCD_DATA2 0x08A8
#define CONTROL_PADCONF_LCD_DATA3 0x08AC
#define CONTROL_PADCONF_LCD_DATA4 0x08B0
#define CONTROL_PADCONF_LCD_DATA5 0x08B4
#define CONTROL_PADCONF_LCD_DATA6 0x08B8
#define CONTROL_PADCONF_LCD_DATA7 0x08BC
#define CONTROL_PADCONF_LCD_DATA8 0x08C0
#define CONTROL_PADCONF_LCD_DATA9 0x08C4
#define CONTROL_PADCONF_LCD_DATA10 0x08C8
#define CONTROL_PADCONF_LCD_DATA11 0x08CC
#define CONTROL_PADCONF_LCD_DATA12 0x08D0
#define CONTROL_PADCONF_LCD_DATA13 0x08D4
#define CONTROL_PADCONF_LCD_DATA14 0x08D8
#define CONTROL_PADCONF_LCD_DATA15 0x08DC
#define CONTROL_PADCONF_LCD_VSYNC 0x08E0
#define CONTROL_PADCONF_LCD_HSYNC 0x08E4
#define CONTROL_PADCONF_LCD_PCLK 0x08E8
#define CONTROL_PADCONF_LCD_AC_BIAS_EN 0x08EC
#define CONTROL_PADCONF_MMC0_DAT3 0x08F0
#define CONTROL_PADCONF_MMC0_DAT2 0x08F4
#define CONTROL_PADCONF_MMC0_DAT1 0x08F8
#define CONTROL_PADCONF_MMC0_DAT0 0x08FC
#define CONTROL_PADCONF_MMC0_CLK 0x0900
#define CONTROL_PADCONF_MMC0_CMD 0x0904
#define CONTROL_PADCONF_MII1_COL 0x0908
#define CONTROL_PADCONF_MII1_CRS 0x090C
#define CONTROL_PADCONF_MII1_RX_ER 0x0910
#define CONTROL_PADCONF_MII1_TX_EN 0x0914
#define CONTROL_PADCONF_MII1_RX_DV 0x0918
#define CONTROL_PADCONF_MII1_TXD3 0x091C
#define CONTROL_PADCONF_MII1_TXD2 0x0920
#define CONTROL_PADCONF_MII1_TXD1 0x0924
#define CONTROL_PADCONF_MII1_TXD0 0x0928
#define CONTROL_PADCONF_MII1_TX_CLK 0x092C
#define CONTROL_PADCONF_MII1_RX_CLK 0x0930
#define CONTROL_PADCONF_MII1_RXD3 0x0934
#define CONTROL_PADCONF_MII1_RXD2 0x0938
#define CONTROL_PADCONF_MII1_RXD1 0x093C
#define CONTROL_PADCONF_MII1_RXD0 0x0940
#define CONTROL_PADCONF_RMII1_REF_CLK 0x0944
#define CONTROL_PADCONF_MDIO 0x0948
#define CONTROL_PADCONF_MDC 0x094C
#define CONTROL_PADCONF_SPI0_SCLK 0x0950
#define CONTROL_PADCONF_SPI0_D0 0x0954
#define CONTROL_PADCONF_SPI0_D1 0x0958
#define CONTROL_PADCONF_SPI0_CS0 0x095C
#define CONTROL_PADCONF_SPI0_CS1 0x0960
#define CONTROL_PADCONF_ECAP0_IN_PWM0_OUT 0x0964
#define CONTROL_PADCONF_UART0_CTSN 0x0968
#define CONTROL_PADCONF_UART0_RTSN 0x096C
#define CONTROL_PADCONF_UART0_RXD 0x0970
#define CONTROL_PADCONF_UART0_TXD 0x0974
#define CONTROL_PADCONF_UART1_CTSN 0x0978
#define CONTROL_PADCONF_UART1_RTSN 0x097C
#define CONTROL_PADCONF_UART1_RXD 0x0980
#define CONTROL_PADCONF_UART1_TXD 0x0984
#define CONTROL_PADCONF_I2C0_SDA 0x0988
#define CONTROL_PADCONF_I2C0_SCL 0x098C
#define CONTROL_PADCONF_MCASP0_ACLKX 0x0990
#define CONTROL_PADCONF_MCASP0_FSX 0x0994
#define CONTROL_PADCONF_MCASP0_AXR0 0x0998
#define CONTROL_PADCONF_MCASP0_AHCLKR 0x099C
#define CONTROL_PADCONF_MCASP0_ACLKR 0x09A0
#define CONTROL_PADCONF_MCASP0_FSR 0x09A4
#define CONTROL_PADCONF_MCASP0_AXR1 0x09A8
#define CONTROL_PADCONF_MCASP0_AHCLKX 0x09AC
#define CONTROL_PADCONF_XDMA_EVENT_INTR0 0x09B0
#define CONTROL_PADCONF_XDMA_EVENT_INTR1 0x09B4
#define CONTROL_PADCONF_WARMRSTN 0x09B8
#define CONTROL_PADCONF_PWRONRSTN 0x09BC
#define CONTROL_PADCONF_EXTINTN 0x09C0
#define CONTROL_PADCONF_XTALIN 0x09C4
#define CONTROL_PADCONF_XTALOUT 0x09C8
#define CONTROL_PADCONF_TMS 0x09D0
#define CONTROL_PADCONF_TDI 0x09D4
#define CONTROL_PADCONF_TDO 0x09D8
#define CONTROL_PADCONF_TCK 0x09DC
#define CONTROL_PADCONF_TRSTN 0x09E0
#define CONTROL_PADCONF_EMU0 0x09E4
#define CONTROL_PADCONF_EMU1 0x09E8
#define CONTROL_PADCONF_RTC_XTALIN 0x09EC
#define CONTROL_PADCONF_RTC_XTALOUT 0x09F0
#define CONTROL_PADCONF_RTC_PWRONRSTN 0x09F8
#define CONTROL_PADCONF_PMIC_POWER_EN 0x09FC
#define CONTROL_PADCONF_EXT_WAKEUP 0x0A00
#define CONTROL_PADCONF_RTC_KALDO_ENN 0x0A04
#define CONTROL_PADCONF_USB0_DM 0x0A08
#define CONTROL_PADCONF_USB0_DP 0x0A0C
#define CONTROL_PADCONF_USB0_CE 0x0A10
#define CONTROL_PADCONF_USB0_ID 0x0A14
#define CONTROL_PADCONF_USB0_VBUS 0x0A18
#define CONTROL_PADCONF_USB0_DRVVBUS 0x0A1C
#define CONTROL_PADCONF_USB1_DM 0x0A20
#define CONTROL_PADCONF_USB1_DP 0x0A24
#define CONTROL_PADCONF_USB1_CE 0x0A28
#define CONTROL_PADCONF_USB1_ID 0x0A2C
#define CONTROL_PADCONF_USB1_VBUS 0x0A30
#define CONTROL_PADCONF_USB1_DRVVBUS 0x0A34
#define CONTROL_PADCONF_DDR_RESETN 0x0A38
#define CONTROL_PADCONF_DDR_CSN0 0x0A3C
#define CONTROL_PADCONF_DDR_CKE 0x0A40
#define CONTROL_PADCONF_DDR_CK 0x0A44
#define CONTROL_PADCONF_DDR_CKN 0x0A48
#define CONTROL_PADCONF_DDR_CASN 0x0A4C
#define CONTROL_PADCONF_DDR_RASN 0x0A50
#define CONTROL_PADCONF_DDR_WEN 0x0A54
#define CONTROL_PADCONF_DDR_BA0 0x0A58
#define CONTROL_PADCONF_DDR_BA1 0x0A5C
#define CONTROL_PADCONF_DDR_BA2 0x0A60
#define CONTROL_PADCONF_DDR_A0 0x0A64
#define CONTROL_PADCONF_DDR_A1 0x0A68
#define CONTROL_PADCONF_DDR_A2 0x0A6C
#define CONTROL_PADCONF_DDR_A3 0x0A70
#define CONTROL_PADCONF_DDR_A4 0x0A74
#define CONTROL_PADCONF_DDR_A5 0x0A78
#define CONTROL_PADCONF_DDR_A6 0x0A7C
#define CONTROL_PADCONF_DDR_A7 0x0A80
#define CONTROL_PADCONF_DDR_A8 0x0A84
#define CONTROL_PADCONF_DDR_A9 0x0A88
#define CONTROL_PADCONF_DDR_A10 0x0A8C
#define CONTROL_PADCONF_DDR_A11 0x0A90
#define CONTROL_PADCONF_DDR_A12 0x0A94
#define CONTROL_PADCONF_DDR_A13 0x0A98
#define CONTROL_PADCONF_DDR_A14 0x0A9C
#define CONTROL_PADCONF_DDR_A15 0x0AA0
#define CONTROL_PADCONF_DDR_ODT 0x0AA4
#define CONTROL_PADCONF_DDR_D0 0x0AA8
#define CONTROL_PADCONF_DDR_D1 0x0AAC
#define CONTROL_PADCONF_DDR_D2 0x0AB0
#define CONTROL_PADCONF_DDR_D3 0x0AB4
#define CONTROL_PADCONF_DDR_D4 0x0AB8
#define CONTROL_PADCONF_DDR_D5 0x0ABC
#define CONTROL_PADCONF_DDR_D6 0x0AC0
#define CONTROL_PADCONF_DDR_D7 0x0AC4
#define CONTROL_PADCONF_DDR_D8 0x0AC8
#define CONTROL_PADCONF_DDR_D9 0x0ACC
#define CONTROL_PADCONF_DDR_D10 0x0AD0
#define CONTROL_PADCONF_DDR_D11 0x0AD4
#define CONTROL_PADCONF_DDR_D12 0x0AD8
#define CONTROL_PADCONF_DDR_D13 0x0ADC
#define CONTROL_PADCONF_DDR_D14 0x0AE0
#define CONTROL_PADCONF_DDR_D15 0x0AE4
#define CONTROL_PADCONF_DDR_DQM0 0x0AE8
#define CONTROL_PADCONF_DDR_DQM1 0x0AEC
#define CONTROL_PADCONF_DDR_DQS0 0x0AF0
#define CONTROL_PADCONF_DDR_DQSN0 0x0AF4
#define CONTROL_PADCONF_DDR_DQS1 0x0AF8
#define CONTROL_PADCONF_DDR_DQSN1 0x0AFC
#define CONTROL_PADCONF_DDR_VREF 0x0B00
#define CONTROL_PADCONF_DDR_VTP 0x0B04
#define CONTROL_PADCONF_AIN7 0x0B10
#define CONTROL_PADCONF_AIN6 0x0B14
#define CONTROL_PADCONF_AIN5 0x0B18
#define CONTROL_PADCONF_AIN4 0x0B1C
#define CONTROL_PADCONF_AIN3 0x0B20
#define CONTROL_PADCONF_AIN2 0x0B24
#define CONTROL_PADCONF_AIN1 0x0B28
#define CONTROL_PADCONF_AIN0 0x0B2C
#define CONTROL_PADCONF_VREFP 0x0B30
#define CONTROL_PADCONF_VREFN 0x0B34
//#define MUX_VAL(OFFSET,VALUE) writel((VALUE), AM335X_CTRL_BASE + (OFFSET));
#define MUX_VAL(OFFSET,VALUE) HWREG(SOC_CONTROL_REGS + (OFFSET)) = (VALUE);
#endif
and the function "PortModeSelect_Ind()" modified as:
void PortRGMIIModeSelect(void)
{
/* Select RGMII, Internal Delay mode */
//HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL) = 0x0A;
HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL) =0x0e; //0x0A;
}
void PortModeSelect_Ind(void)
{
PortRGMIIModeSelect();
}
and I modified some statements in funtion "static void cpgmacMacOpen(Cpsw3gPort *hPort)" as follow:
/* Finally Set the Mac Control register. Enable MII */
// CPSWSlGMIIEnable(cpsw3gCfg->baseConfig.port[instId].sliver_base); //COMENTED BY TANG 20140414
/* Finally Set the Mac Control register. Enable RGMII */
CPSWSlRGMIIEnable(cpsw3gCfg->baseConfig.port[instId].sliver_base); //ADDED BY TANG 20140414
and funtion "cpsw3g_SetMacCfg()" as follow:
/* commented by tang 20140414
if (macInitCfg & CPSW_CONFIG_MODEFLG_GIGABIT)
CPSWSlGMIIEnable(localDev.Config.baseConfig.port[macNo].sliver_base);
if (macInitCfg & CPSW_CONFIG_MODEFLG_IFCTLA)
CPSWSlIFCTLAEnable(localDev.Config.baseConfig.port[macNo].sliver_base);
if (macInitCfg & CPSW_CONFIG_MODEFLG_FULLDUPLEX)
CPSWSlFullDuplexEnable(localDev.Config.baseConfig.port[macNo].sliver_base);
*/
//added by tang 20140414
CPSWSlRGMIIEnable(localDev.Config.baseConfig.port[macNo].sliver_base);
CPSWSlFullDuplexEnable(localDev.Config.baseConfig.port[macNo].sliver_base);
When I use software "wireshark" to catch packets, no packets from am3359 occoured.
the CCS console display:
[CortxA8] enter main()
Network Added: If-1:192.168.1.10
enter taskNetAppFxn()
00010.000 TCP: Retransmit Timeout
00034.000 TCP: Retransmit Timeout
00079.000 TCP: Keep Timeout
failed connect (65)
exit taskNetAppFxn()
Hello,
I don't see much wrong here(w.r.to CPSW configuration), I can't comment on the pinmux.
EVM-SK uses RGMII, and it has support in Starterware. You can refer this for configuring CPSW.
Also, are any of the RX/TX interrupts getting hit? If no, then there is some basic config/pinmux settings missing.
Regards,
Vinesh
Vinesh,
I just want to know how to modify the cpsw ndk driver to adapt to my custom board's RGMII interface,thanks ! anybody else can help me?
Regards,
Rolan
Dear,
I add statements as follow in function "cpsw3g_Update_Phystatus()" of file " cpsw_impl.c":
if (gmacObject->PhySpeed == 2)
{
macControl |= CPSW_SL_MACCONTROL_GIG;
}
and my custom board can work correctly, is this a bug of am335x NDK CPSW DRIVER?
Regards,
Rolan
Rolan,
Glad you got it working.
Yes, it seems to be a bug in the CPSW driver. GIG(1000Mbps) mode is something we haven't supported yet. Only MII Mode(10/100 HD and FD) are supported.
Regards,
Vinesh
