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AM3352 resetin_out

Other Parts Discussed in Thread: TPS65910, AM3352, SN74LVC1G07, TPS62142

Hi,

We are planning to give the manual reset input and NRESPWROn from TPS65910 as PORz for AM3352. And then RESETIN_OUT will be used as reset for other components present on board.  I have one doubt -

Does this RESETIN_OUT pin remains low from start (when the AM3352 is powered up)?

If it goes high in start even for a small duration this will not act as power on reset for other components on board. Also as it becomes a open drain output with a weak internal pull up after the PORZ is high, I can't provide any external pull down on this pin. 

Thanks & Regards,

Nikhil

  • We are in the process of adding the following Advisory to the AM335x Silicon Errata.  I think this should answer your question.

    Advisory 1.0.TBD          WARMRSTn: Terminal may Source a short-duration Logic-High Pulse during the Power-up Sequence

    Revision(s) Affected:      2.1, 2.0, 1.0

    Details:

    The WARMRSTn output buffer is implemented with a push-pull 3-state output buffer that has been configured to operate as an open-drain output.  The state of the output buffer is not determined until VDDS, VDDSHV6, and VDD_CORE supplies have ramped to their recommended operating voltage.  This may allow the output buffer to source a short-duration logic-high pulse while power supplies are ramping.

    Workaround:

    If WARMRSTn is used as an input only:  If an external device could be driving warm reset low when the short-duration logic-high pulse is being sourced by AM335x, a 75 ohm series resistor should be inserted in the path to limit the current.

    If WARMRSTn is used as an output: If a short-duration logic-high pulse during power-up could cause an issue with other portions of the system, external components could be used to hold the warm reset signal low during power-up and limit the current.

     Insert Figure from attached PDF file.

    5545.AM335x warm reset cicuit.pdf

    This circuit is one example how an open-drain buffer and series resistor could be used to ensure peripheral devices would never see the short-duration logic-high pulse.  If VDDSHV6 is configured for 3.3 volt operation, VDD_EARLY can be a 3.3 or 5.0 volt power source that is applied before the 1.8 volt VDDS supply.  If VDDSHV6 is configured for 1.8 volt operation, VDD_EARLY should be connected to the 1.8 volt VDDS supply.

    Regards,
    Paul

  • Thanks Paul, we will follow this circuit.

    Regards,

    Nikhil

  • Hi Paul,

    I was going through the scheme you suggested. In our case VDDSHV is configured as 3.3V. You have suggested that "VDD_EARLY can be a 3.3 or 5.0 volt power source that is applied before the 1.8 volt VDDS supply".

    In my system 5V comes earliest. According to the open drain buffer datasheet the SN74LVC1G07 for 5V input the VIH min level is 0.7xVCC = 3.5V. But the NRESPWRON level of PMIC TPS65910A3 the VOH level is VDDIO-0.2 (3V). Even if this signal goes till maximum voltage level 3.3V it will not be able to make the open drain output high/open drain.

    Please suggest what should be done in this case?

    Also can you provide the drive current of warm reset pin when it is driving the output High. 

    Thanks & regards,

    Nikhil 

  • Good catch.

    You could add a separate 3.3 volt regulator for this buffer, but this may be over-kill.  A much simpler and cheaper option would be inserting a diode in series with the open-drain buffer power supply terminal to reduce the operating voltage to about 4.3 volts which will reduce VIH min to 3.0 volts (0.7*4.3).  If you use this option, a high value resistor may need to be connected from the buffer power supply terminal to ground to keep the buffer supply voltage pulled down to one diode drop below 5.0 volts.

    I noticed something else you may want to change. The value of the series resistor connecting WARMRSTn to the buffer output should be increased from 75 ohms to 110 ohms to limit the current to less than 32 mA which is the maximum rated output current of the buffer.

    Regards,
    Paul

  • Hi Paul,

    On our board instead of using this open drain buffer we are thinking of another approach. We have a SMPS (TPS62142) for generating the 3.3V supply. We will give the reset from PMIC to AM3352 PORZ.

    The enable of SMPS is connected to a 3.3V generated by the PMIC. And the power good of SMPS (open drain) is tied to the RESETIN_OUT of AM3352 as suggested by you. So initially the power good will remain low till 100µs after the 3.3V from PMIC comes up. So it will maintain the reset output from AM3352 low. 

    We don't know the exact time for which this high pulse on AM3352 comes so we are asumming that this time (for which power good is low) should be sufficient for negating this pulse. Please confirm if my understanding is correct.

    Also the drain current for SMPS power good is 2mA max. So we are thinking of increasing the series resistor from 75Ω to around 2KΩ so that the current remains below 2mA. Please let us know if you foresee any issues in this reset scheme.

    Thanks & regards,

    Nikhil 

  • The most likely time were the AM335x WARMRSTn terminal could drive a logic-high pulse begins as soon as VDDSHV6 begins to ramp and remains in that state until VDD_CORE ramps to the recommended operating voltage.

    So the TPS62142 will need to powered up before VDDSHV6 begins to ramp for this to work.

    The AM335x WARMRSTn may not be able to pull the reset signal attached to peripherals low enough to be a valid logic low with a 2 kohm series resistor since the series resistor and any pull-up on the other side of the series resistor will create a voltage divider.

    Regards,
    Paul