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DM3730 DRAM overshoot/undershoot tolerance?

Andrew5821
Genius 4555 points
Other Parts Discussed in Thread: DM3730

The DM3730CUS datasheet per the "Other Balls" specification says that pins should be keep with 0.3V of the rails.  This is difficult to do with a DRAM bus.  The JESD209B specification for mDDR says that overshoot/undershoot can be 0.5V as long as the integrated area of the overshoot/undershoot is less that 3V-ns.  This also appears to be near what Micron states (1V for <3ns).  So are the DRAM controller I/O on the DM3730 compliant to the JEDEC specification?  I'm seeing about 360mV of undershoot and no overshoot.

  • 0
    Genius 4555 points

    Nobody at TI knows...?

  • 0
    TI__Mastermind 23155 points

    Andrew

    Table 3-5 covers the DC Electical Characteristics. 

    VIH for Other Balls should not be greater than VDDS + 0.3V in a steady state.

      Paul

  • 0 in reply to PaulM
    Genius 4555 points

    Understood, but I'm concerned about the transient state so you don't punch through the gate of some transistor or overheat a clamping diode.

  • 0 in reply to Andrew5821
    TI__Genius 9575 points

    From a reliability stand point, If the transient overshoot/undershoot is <20% of the nominal supply / <20% duty cycle, there should not be issue. What is the OS/US that you measure?

  • 0 in reply to sivak
    Genius 4555 points

    I'm getting less than 100mV OS and 300-450mV US for ~2ns on the OMAP end of the bus when the DRAM is driving.  There is very little OS/US on the DRAM end when the OMAP drives the bus.  I'm guessing the DRAM on this board has a stronger than typical pulldown driver.  I can confirms this by at the rise time on the receiver end being 1.4ns while the fall time is 900ps.  When looking at the DRAM pin when it drives the bus, I also notice that the midpoint plateau/hitch on the falling edge waveform is not at the midpoint like it is on the rising edge, but at a slightly lower voltage.  

    DRAM is set for 3/4 drive, 1/2 drive did not work.  OMAP has 22ohms of source termination as close to the part as you can get.  Everything is routed per the DRAM layout guidelines in the DM3730 datasheet.

  • 0 in reply to Andrew5821
    Genius 4555 points

    No offense, but I do find it a bit frustrating that I can't get an answer other than a different way of restating the DC operating characteristics of the datasheet.  The fab and silicon designer should  have this information readily available!  Altera and Micron clearly specify AC operating conditions.  Altera even goes as far as projecting a device lifetime with various OS/US conditions.