ddr2 interface to am335x

You don't directly program the DDR2 mode registers.  Writing to the SDRAM_CONFIG register of the AM335x will trigger an initialization sequence to the DDR2.  If you compare the fields you would program in the DDR2 with the SDRAM_CONFIG register you'll notice that all the important ones are part of the SDRAM_CONFIG register.

Hi,

Thank You. I got your point. I have compared the things.

Now there are a set of command functions to activate bank, read, write,burst read with auto precharge etc.

For eg. To issue read command- I should signal the following : [CS ="L",RAS ="H",CAS ="L", WE ="H", BA0, BA1, BA2=Bank, A10="L", A0 to A9=Column Address]. How to give signal from EMIF controller to DDR Memory. All of these are Output signals from EMIF controller. To make CS as low, what should i do? How to send signal through a particular pin?

Looking forward for your reply.

Regards,

Sudha J

Once you've configured the controller you don't have to do anything further.  If you look at the device memory map you'll see 1GB of external memory mapped to address 0x80000000.  Performing a read or write to that memory space with the CPU (or DMA, etc) will cause the EMIF to transparently perform the necessary commands.  So for example, if you connect JTAG and open a memory window to address 0x80000000 you should be able to force activity by writing to the memory window, refreshing the memory window, etc.

Hi, 

In the ddr2 data sheet, there is some initialiation sequence. How to do that?

1. Apply power and attempt to maintain CKE below 0.2 × VDDQ and ODT*1 at a LOW state (all other
inputs may be undefined.) Either one of the following sequence is required for Power-up.
A. The VDD voltage ramp time must be no greater than 200 mS from when VDD ramps from 300
mV to VDD min; and during the VDD voltage ramp, |VDD -VDDQ| ≤ 0.3 volts.
 VDD, VDDL and VDDQ are driven from a single power converter output
 VTT is limited to 0.95V max
 VREF
*2 tracks VDDQ/2
 VDDQ ≥ VREF must be met at all times
B. Voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid
DRAM latch-up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be
maintained and is applicable to both AC and DC levels until the ramping of the supply voltages
is complete.
 Apply VDD/VDDL
*3 before or at the same time as VDDQ
 Apply VDDQ
*4 before or at the same time as VTT
 VREF
*2 tracks VDDQ/2
 VDDQ ≥ VREF must be met at all times.
2. Start Clock and maintain stable condition for 200 μS (min.).
3. After stable power and clock (CLK,CLK ), apply NOP or Deselect and take CKE HIGH.
4. Wait minimum of 400 nS then issue precharge all command. NOP or Deselect applied during 400
nS period.
5. Issue an EMRS command to EMR (2). (To issue EMRS command to EMR (2), provide LOW to
BA0, HIGH to BA1, LOW to BA2.)
6. Issue an EMRS command to EMR (3). (To issue EMRS command to EMR (3), provide HIGH to
BA0 and BA1, LOW to BA2.)
7. Issue EMRS to enable DLL. (To issue DLL Enable command, provide LOW to A0, HIGH to BA0
and LOW to BA1-BA2 and A13. And A9=A8=A7=LOW must be used when issuing this command.)
8. Issue a Mode Register Set command for DLL reset. (To issue DLL Reset command, provide HIGH
to A8 and LOW to BA0-BA2 and A13.)
9. Issue a precharge all command.
10. Issue 2 or more Auto Refresh commands.
11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating
parameters without resetting the DLL.)
12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment).
If OCD calibration is not used, EMRS to EMR (1) to set OCD Calibration Default
(A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit OCD Calibration Mode
(A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).
13. The DDR2 SDRAM is now ready for normal operation.

Regards,

J Sudha

You're making this vastly more complicated than it should be.  TI's design team has precisely followed the JEDEC specifications to implement all the appropriate steps for initialization.  The voltage related items you mention above obviously need to be handled by your PCB/power design.  The actual initialization sequence is handled by the EMIF in compliance with the corresponding JEDEC standard.  The AM335x supports LPDDR, DDR2, and DDR3(L).  As long as you have obeyed all the AM335x data manual requirements with respect to layout, and you have properly programmed the EMIF's timing related registers, all of this will be handled for you automatically.  You need not be concerned with bus level commands as that's all "under the hood" of the EMIF.

Thank You. I am cleared with my doubts.

Regards,

J Sudha