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[AM335x] EDMA (TC) priority to EMIF

Naoki Kawada
Guru 19890 points

Hi,

Just a quick question.

MREQPRIO register looks like the register to configure the priority of master ports for EMIF, but I could not find the register fields for EDMA TCs. Can I understand there is no configuration for that ? 

Best Regards,
Kawada

  • 0
    TI__Guru**** 393215 points

    Hi Kawada-san,

    From section 11.1 of the AM335X TRM Rev. K:

    "The EDMA3 channel controller serves as the user interface for the EDMA3 controller. The EDMA3CC includes parameter RAM (PaRAM), channel control registers, and interrupt control registers. The EDMA3CC serves to prioritize incoming software requests or events from peripherals and submits transfer requests (TRs) to the transfer controller.
    The EDMA3 transfer controllers are slaves to the EDMA3 channel controller that is responsible for data
    movement. The transfer controller issues read/write commands to the source and destination addresses
    that are programmed for a given transfer. The operation is transparent to user."
  • 0 in reply to Biser Gatchev-XID
    Guru 19890 points

    Hi Biser

    EDMA TCs are slaves to the EDMA CC, but they should be masters to EMIF because they are transfer initiators, right ?. So I thought there should be some configurations in MREQPRIO register, however, there were no fields to configure EDMA TC priority to EMIF. It is ok for me even If there is no configurations for EDMA TCs in MREQPRIO register. This is just a confirmation to understand MREQPRIO register correctly.

    Regards,
    Kawada

  • 0 in reply to Naoki Kawada
    Guru 19890 points

    Any update on this ?

  • 0 in reply to Naoki Kawada
    TI__Guru* 78415 points

    Hi Kawada-san

    For EDMA TC , the MREQPRIO is driven directly the QUEPRI register. This register is located in the EDMACC memory map. The QUEPRI register is for EDMA CC queue priority and there is a 1 to 1 mapping of an EDMA CC Qx to EDMA TCx . For all other masters (except LCD and EDMA TCs) this priority is configurable via the MREQPRIO register (in the control module).  For LCD , mreqprio is configurable via the  LCDDMA_CTRL. PRIO register bit fields

    Hope this helps.

    Regards

    Mukul

     

  • 0 in reply to Mukul Bhatnagar
    Guru 19890 points

    Hi Mukul,

    Thanks for your reply. Ok. Please let me confirm more things about MREQPRIO 0/1 registers. 
    There are some writable 3bit fields in these registers, but there is no description about the values for that. Can I understand 0 is for the highest priority and 7 is for the lowest one ? Also, I could not understand the difference between sab_init1 and sab_init0. As for exp field, I don't know what masters are belonging to exp (Expansion Initiator). Could you please explain ?

    Best Regards,
    Kawada

  • 0 in reply to Naoki Kawada
    TI__Guru* 78415 points

    Naoki Kawada said:
    Can I understand 0 is for the highest priority and 7 is for the lowest one ?

    That is correct. 

    Naoki Kawada said:
    Also, I could not understand the difference between sab_init1 and sab_init0.

    This is for priority configuration of the MPU ports, if you look in the Interconnect chapter, these are Cortex-A8 MPUSS 128-bit initiator port0 and 64-bit initiator port1

    Naoki Kawada said:
    As for exp field, I don't know what masters are belonging to exp (Expansion Initiator).

    I need to investigate further on this. As far as I can tell, this should be a don't care for AM335x. I will reconfirm and update this post

    Regards

    Mukul

  • 0 in reply to Mukul Bhatnagar
    Guru 19890 points

    Thanks, Mukul.

    As for the last question, please let me know once you get the findings.

    Best Regards,
    Kawada

  • 0 in reply to Naoki Kawada
    TI__Guru* 78415 points

    Hi Kawada-san

    I confirmed on this, exp bit fields in MREQ register is a "don't care" , and read/writes to this register will not change/impact any master priority. This port is tied of in AM335x L3 interconnect and no master is attached to it.

    Regards

    Mukul 

  • 0 in reply to Mukul Bhatnagar
    Guru 19890 points

    Hi Mukul,

    Thanks for the confirmation. I understood. 
    If possible, I would like you to raise a request to right person to revise the description in TRM for the next release.

    Again, thanks for all your helps.

    Best Regards,
    Kawada

  • 0 in reply to Naoki Kawada
    Mastermind 8020 points

    Naoki Kawada said:
    I don't know what masters are belonging to exp (Expansion Initiator)

    Many recent SoC have references to an Expansion Port, with basically no info other than that it's a 128-bit initiator and 128-bit target on the L3-Fast interconnect.  My guess would be that it's something similar to the OMAP4's chip-to-chip interface, meant to allow an external chip direct interconnect access (e.g. to share RAM).  In any case, the lack of documentation makes evident it's not available except probably for sufficiently big customers.

  • 0 in reply to Matthijs van Duin
    TI__Guru* 78415 points

    Incase of AM335x this port is not tied to anything in design, so it is not a matter of broad vs big customer etc. 

    I have filed a litbug to have this fixed in the next rev of the doc.

    Thanks. 

    Mukul

  • 0 in reply to Mukul Bhatnagar
    Mastermind 8020 points

    Mukul Bhatnagar said:
    Incase of AM335x this port is not tied to anything in design, so it is not a matter of broad vs big customer etc.

    Thank you for clarifying!