I am trying to connect a custom LCD to the BBB and am unable to get it to display 24 bit video.
I attempted to modify the device tree using the LCD7 overlay as a starting point (unmodified works to display 16 bit video on my LCD) by adding the 8 additional LCD pins and changing bpp from 16 to 24.
Unfortunately, both fbset and a peek at the LCDC_RASTER_CTRL_REG show it is still running in 16 bit mode:
fbset
mode "800x480"
geometry 800 480 800 480 16
timings 0 0 0 0 0 0 0
accel true
rgba 5/11,6/5,5/0,0/0
endmode
devmem2 0x4830e028 w
Value at address 0x4830E028 (0xb6fd0028): 0xA00081
Looking on-line I see some mention that the tilcdc only supports 16 bit video. But looking in the source (from http://lxr.free-electrons.com/source/drivers/gpu/drm/tilcdc/tilcdc_crtc.c) I see that it supports bpp=24 "if (priv->rev == 2)", so I'm hoping that the limitation was old information.
There isn't much information in dmesg:
[ 7.259172] tilcdc 4830e000.fb: Power GPIO active high, initial state set to high
[ 7.267346] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[ 7.274327] [drm] No driver support for vblank timestamp query.
[ 7.282706] mmc0: host does not support reading read-only switch. assuming write-enable.
[ 7.284963] mmc0: new high speed SDHC card at address 0007
[ 7.285459] mmcblk0: mmc0:0007 SD08G 7.42 GiB
[ 7.286898] mmcblk0: p1 p2
[ 7.293286] Console: switching to colour frame buffer device 100x30
[ 7.331097] tilcdc 4830e000.fb: fb0: frame buffer device
[ 7.338105] tilcdc 4830e000.fb: registered panic notifier
[ 7.345141] [drm] Initialized tilcdc 1.0.0 20121205 on minor 0
So, does anyone know if this can/should work with further boot/device tree configurations that I'm not doing? Or if not, what should be done differently if I need to build the kernel?
P.S. Here's the device tree I'm using:
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";
pinctrl-0 = <&userled_pins>;
...
bone_lcd7_cape_lcd_pins: pinmux_bone_lcd7_cape_lcd_pins {
pinctrl-single,pins = <
0x150 0x07 /* spi0_sclk.gpio0_2, OUTPUT | MODE7 - AVDD_EN */
0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0x3c 0x09 /* lcd_data16.lcd_data16, OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0x38 0x09 /* lcd_data17.lcd_data17, OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0x34 0x09 /* lcd_data18.lcd_data18, OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0x30 0x09 /* lcd_data19.lcd_data19, OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0x2c 0x09 /* lcd_data20.lcd_data20, OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0x28 0x09 /* lcd_data21.lcd_data21, OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0x24 0x09 /* lcd_data22.lcd_data22, OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0x20 0x09 /* lcd_data23.lcd_data23, OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
>;
};
};
ocp: ocp {
...
/* Settings for ThreeFive S9700RTWV35TR / LCD7 cape: */
panel {
compatible = "tilcdc,panel";
pinctrl-names = "default";
pinctrl-0 = <&bone_lcd7_cape_lcd_pins>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <24>;
fdd = <0x80>;
tft-alt-mode = <0>;
stn-565-mode = <0>;
mono-8bit-mode = <0>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
invert-pxl-clk;
};
display-timings {
native-mode = <&timing0>;
timing0: 800x480 {
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <40>;
hsync-len = <48>;
vback-porch = <30>;
vfront-porch = <13>;
vsync-len = <3>;
clock-frequency = <30000000>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
Thanks in advance for any pointers!
