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using only port0 for ethercat on sitara

Other Parts Discussed in Thread: AM3357, SYSBIOS

Hi.

We designed a board based upon Am3357; the board has only two ethernet PHYs (PHY0 and PHY1, at address 0x00 and 0x01 respectively) which can be multiplexed the following ways:
1 - CPSW_RMII1 --> PHY0   and   CPSW_RMII2 --> PHY1
2 - PRU_MII0   --> PHY0   and   PRU_MII1   --> PHY1
3 - PRU_MII0   --> PHY0   and   CPSW_RMII2 --> PHY1

Configurations 1 and 2 work perfectly; configuration 2 works when both ECAT_IN (PHY0) and ECAT_OUT (PHY1) are actually connected to the EtherCAT network and works also when only ECAT_IN (PHY0) is actually connected (that is, my Sitara is the last node in the network).
I'using SDK 1.1.0.4 (the last released by TI - long time ago, let me say).

I'm trying to use mixed configuration 3, but it seems PRU firmware is not happy with it.
I've bypassed all MDIO operations with PHY1 (during initialization of EtherCAT stack and when handling leds), of course.
Is there some way to tell the firmware running on PRUs that PHY1 is not present? Maybe writing a magic number in register 0x0E09 (Port1 PHY address) ...

Thank you for your help.

Mario

 

  • Hi Mario,

    I will bring this to the attention of the factory team.

  • Hi,

    Mario Giovanni Casali said:

    We designed a board based upon Am3357; the board has only two ethernet PHYs (PHY0 and PHY1, at address 0x00 and 0x01 respectively) which can be multiplexed the following ways:

    3 - PRU_MII0   --> PHY0   and   CPSW_RMII2 --> PHY1

    I'm trying to use mixed configuration 3, but it seems PRU firmware is not happy with it.

    I've bypassed all MDIO operations with PHY1 (during initialization of EtherCAT stack and when handling leds), of course.
    Is there some way to tell the firmware running on PRUs that PHY1 is not present? Maybe writing a magic number in register 0x0E09 (Port1 PHY address) ...

    If you do not initialize 0xE09, it will be zero by default. This will confuse firmware as it looks at PHY address 0 for LINK state and it will be UP (PRU_MII0). Suggest not to bypass the init code in SDK, but change Port1 address to non-existent one, say like 3 or 4

  • Hi Pratheesh.

    I changed a couple of lines in function bsp_init setting 0x04 as PhyAddr of second (non-existent) port:

    ...
    mdioParamsInit.addr0 =                        TIESC_MDIO_PHY0_ADDR;
    mdioParamsInit.addr1 = fUseEcatOutConnector ? TIESC_MDIO_PHY1_ADDR : 0x04;  // <--
    ...

    and by-passed explicit mdio operations with phy1 (just not to waste time trying to talk to air): all seems to work fine in my mixed configuration (one ECAT_IN port and one normal Ethernet port).

    Thank you very much, indeed!

    I suppose I have also found a bug in function bsp_pruss_mdio_init; let me know if I'm right or wrong; my bux-fix follows:

    ...
    #if 0
    bsp_write_byte((pmdio_params->link0pol << pmdio_params->addr0) |
                   (pmdio_params->link1pol << pmdio_params->addr1),

                   ESC_ADDR_TI_PHY_LINK_POLARITY);
    #else
    //
    // See description of register 0x0E0A of TI-ESC in
    // "AM335x EtherCAT firmware API Guide" included in SDK 1.1.0.4
    //
    bsp_write_byte((pmdio_params->link0pol << 0) |
                   (pmdio_params->link1pol << 1), ESC_ADDR_TI_PHY_LINK_POLARITY);
    #endif
    ...

    Since my phys' addresses are 0x00 and 0x01, I had no problem at all; if I'm right, however, problems might arise with TI ICE boards ...

    Do you know when a new release of Sitara SDK will be available?
    Will that new release support more recent versions of sysbios and xdc? Maybe ti-rtos for sitara?

    Thank you again.

    Mario

     

  • Hi,

    Mario Giovanni Casali said:

    I'using SDK 1.1.0.4 (the last released by TI - long time ago, let me say).

    New version just got released, http://downloads.ti.com/sitara_indus/esd/AM335x_SYSBIOS_Industrial_SDK/latest/index_FDS.html

  • Hi Pratheesh.

    Thank you for this info. I've been checking http://www.ti.com/tool/sysbiossdk-ind-sitara every days for months, but sdk 1.1.0.4 is still shown. Your link is ok and I already downloaded both sdk 1.1.0.5 and bios 6.40.03.39 and xdc_tools 3.30.04.52 cores (what's the right one for CCSV6 under Windows? with or without jre?); I will shortly look for a compatible UIA and will try to upgrade my applications ...

    One more question: both bios and xdc are newest than the corresponding products is TI-RTOS for Sitara 2.00.01.23 (the only TI-RTOS for Sitara ever released, as far as I know); is there a new "hidden" release? is a new release going to be available in a short time?

    Thank you.

    Mario

  • Hi,

    Mario Giovanni Casali said:

    Your link is ok and I already downloaded both sdk 1.1.0.5 and bios 6.40.03.39 and xdc_tools 3.30.04.52 cores (what's the right one for CCSV6 under Windows? with or without jre?); I will shortly look for a compatible UIA and will try to upgrade my applications ...

    I have used without JRE in Windows and it works.

    Mario Giovanni Casali said:

    One more question: both bios and xdc are newest than the corresponding products is TI-RTOS for Sitara 2.00.01.23 (the only TI-RTOS for Sitara ever released, as far as I know); is there a new "hidden" release? is a new release going to be available in a short time?

    AFAIK no official TI-RTOS drivers planned for Sitara. Current release is SYS/BIOS kernel + XDC tool combo. For Industrial SDK - we normally use the latest version of CCS, XDC tools and SYS/BIOS available