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Jitter tolerance of rmii1_refclk on AM3352

Guru 16800 points
Other Parts Discussed in Thread: AM3352

Hello,

Please let me know the jitter tolerance of rmii1_refclk on AM3352.
AM3352 and Ether PHY are connected by RMII, and then rmii1_refclk is used as input.
Ether PHY output the reference clock to rmii1_refclk of AM3352.
I want to know whether AM3352 can tolerate +10ps and -8ps jitter.

Best Regards,

Nomoto

  • Hi Nomoto-san,

    Table 7-13 in the AM335X Datasheet Rev. G specifies the RMII reference input clock cycle time to be between 19.999 and 20.001ns.

  • Hello Biser-san,

    Thank you for your reply.
    Does the parameter include the jitter?

    Best Regards,

    Nomoto

  • The RMII specification states that the REF_CLK frequency shall be 50 MHz +/- 50 ppm with a duty cycle between 35% and 65% inclusive. There is no jitter requirement there. From internal discussions I know that it's recommended to use an external low-jitter oscillator for reference clock source to both the PHY and the AM335X RMII port.

  • Hello Biser-san,

    I want to know the concrete specification of the jitter tolerance for the reference clock.
    Could you define the specification?

    Best Regards.

    Nomoto

  • No, there isn't any precise data.

  • As Biser mentioned, there is no precise recommendation for this...there are simply too many variables that affect the overall performance of the interface to define a specific number;  what works for one solution may not work for another. Also, Ethernet is inherently robust from a protocol perspective, so it may be acceptable in some use-cases to drop a small percentage of packets due to jitter-induced errors.

    Because Ethernet is a packet based interface, it is sensitive not only to peak-to-peak jitter, but also to n-cycle jitter. In fact, our internal RMII testing revealed that the latter is much more important than the former with regard to impact on packet loss % when tested across all legal packet sizes. 

    To answer your question as best I can, empirical data from observations of our General Purpose EVM show that +/-10ps of p2p jitter and <350ps of n-cycle (where n=512) jitter resulted in zero packet loss when tested against a scenario containing 15 million Tx+Rx packets of random size (min to max) containing randomized data. This should not be construed as a concrete recommendation for all designs and performance requirements, but it should provide an idea of what was required in the context of our use-case.

  • Hello,

    Thank you for your reply.
    The reason why I asked you above question, I need to confirm whether the jitter influences the my customer's problem.
    On my customer's site, the periodic packet loss occurs when PC sends PING to AM3352.
    However, I think AM3352 has no problem due to your suggestions and I want to prove it logically.
    Could you show me the Ether MAC architecture and what modules are activated by reference clock?

    Best Regards,

    Nomoto