Dear all,
Good Morning. In the present project we are using AM3352 ARM processor with DDR3 Interface(ISSI make IS43TR16256A-125KBLI). We have a small doubt w.r.t register setting for SDRAM configuration. See the below snapshot(TRM page no : 594),
Bit field(28-27) --> Internal bank address will be assigned from either lower OCP address/Higher OCP address to DDR3 address mapping depends upon the bit field setting. What we need to set( either 00,01,10,11) for proper SDRAM configuration and what they are trying to say about OCP address???.
Waiting for your reply.
Regards,
Saravanan.K
