Hi,
While probing the 4-wire lines in the idle state, i am getting high on XL line (AIN0) and all the other three lines are in the low state. Is it possible to switch the levels by software in the idle state?
Regards,
Sithara S.
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Hi,
While probing the 4-wire lines in the idle state, i am getting high on XL line (AIN0) and all the other three lines are in the low state. Is it possible to switch the levels by software in the idle state?
Regards,
Sithara S.
Hi Sithara,
What software are you using? What do you mean by idle state?
If you look at Figure 12-2 in the AM335X TRM you will see some signals that control the TSC switches (YPPSW, XNPSW, XPPSW, WPNSW, YNNSW, YPNSW, XNNSW). The IDLECONFIG Register has bitfields that can control these switches. Opposing switches on the same AIN line must never be turned on at the same time.
uhtis said:If XP is high at IDLE step, hope it is possible to change it to low and make YP high?
You can see from the figure that there is no low-side switch for XP. I don't have information about HHV.
I don't understand what is the purpose of these questions. Can you explain please?
It is mentioned that the TSC switches can be configured. But whatever state we have configured, it depends on the state of the control signal, HHV, which is unknown. The NAND and AND gates in the figure 12-2 ic controlled by this signal. If HHV is fixed then how does the changes we do in software gets reflected?
I didn't say HHV is fixed. I said I don't have information about this signal - where it comes from and how it's controlled.
The HHV signal is high while PWRONRSTn is held low. The purpose of this signal is insure the FETs driving the AIN signals do not turn on until TSC is reset.
The pen-up/pen-down interrupt which is generated from the AIN0 input while operating in 4-wire mode assumes a fixed polarity so can not change the idle state.
Regards,
Paul
I am not clear about the TSC module working. So i was trying to understand the behaviour of TSC module by probing the 4-wire signals in the idle state.
We appreciate your patience, our apps team will be replying to your post soon.
My reply below is from the hardware perspective. I cannot comment how this is done in various software drivers.
The FETs are controlled by their respective bits in each STEPCONFIG register.
Bit 11 is used to control the VSSA FET connected to AIN4.
Bit 10 is used to control the VSSA FET connected to AIN2.
Bit 9 is used to control the VDDA FET connected to AIN1.
Bit 8 is used to control the VSSA FET connected to AIN3.
Bit 7 is used to control the VDDA FET connected to AIN2.
Bit 6 is used to control the VSSA FET connected to AIN1.
Bit 5 is used to control the VDDA FET connected to AIN0.
When set to '1', the respective FET is on.
When set to '0', the respective FET is off.
Regards,
Paul
Dear All,
Thanks for your response.
In the patch from TI (with TS_CHARGE_STEPCONFIG same as IDLE_CONFIG) , the values was..
X readout ---->0x40192
Y readout----->0x100072
Z1 ------>0x400D2
Z2 ------>0x1C00D2
The Z1 and Z2 values seems to be wrong in the patch. Please have a look into that.
We have changed the Z1 and Z2 readout step register values as 0x100132 and Z2 as 0x80132.
Now we have to check the pressure threshold value and the ADC delay values (open and sample).
How to set the threshold value ?
uhtis said:Dear All,
Thanks for your response.
In the patch from TI (with TS_CHARGE_STEPCONFIG same as IDLE_CONFIG) , the values was..
X readout ---->0x40192
Y readout----->0x100072
Z1 ------>0x400D2
Z2 ------>0x1C00D2
The Z1 and Z2 values seems to be wrong in the patch. Please have a look into that.
We have changed the Z1 and Z2 readout step register values as 0x100132 and Z2 as 0x80132.
Now we have to check the pressure threshold value and the ADC delay values (open and sample).
How to set the threshold value ?
Can you be more specific about "the patch from TI"? Are you referring to the patch set for SDK 7.00 that I posted here:
http://e2e.ti.com/support/arm/sitara_arm/f/791/p/319613/1298838.aspx#1298838
What Linux SDK are you using and which patch are you referring to?
In any case, my recommendation would be to get SDK 7.00 and apply the patch from my post above. I spent two weeks going through every bit and every calculation to try and get everything perfect. I know of at least one customer that has successfully integrated the patches.
My recollection is that the Z calculation may have been wrong in SDK 6.00. I'm pretty sure that was one of the items updated in the base SDK 7.00 release.
Oops -- I pointed to my original patch set instead of the v2 patch set. Here's the right link (further down in the same thread):
http://e2e.ti.com/support/arm/sitara_arm/f/791/p/319613/1308705.aspx#1308705
uhtis said:But the Z1 and Z2 values of 0x400D2 and 0x1C00D2 seems to be wrong. Could you please confirm?
Those are correct. Do you have your hardware hooked up properly:
At some point the device tree introduced configurability of these inputs, but that should not have been done. This configuration is required by the hardware. You must use the configuration above in conjunction with ti,wire-config = <0x00 0x11 0x22 0x33> in the device tree file.