Hi,
I have one question regarding the read cycle timing of AM3517 GPMC.
The current setting of GPMC configuration registers are the following.
OUTREG32(&pGpmc->GPMC_CONFIG1_2, 0x00001000);
OUTREG32(&pGpmc->GPMC_CONFIG2_2, 0x00181602);
OUTREG32(&pGpmc->GPMC_CONFIG3_2, 0x00010100);
OUTREG32(&pGpmc->GPMC_CONFIG4_2, 0x14061406);
OUTREG32(&pGpmc->GPMC_CONFIG5_2, 0x01141A1C);
OUTREG32(&pGpmc->GPMC_CONFIG7_2, 0x00000F46);
As you know, Config5 register [4:0] bits shows RDCYCLETIME.
Its value is 0x1C(28) as the following.
Bits Field Name Type Value Note
4:0 RDCYCLETIME RW 0x1C (28)d
GPMC_FCLK is 166MHz(6.02ns).
In the above setting, customer checked the read cycle time.
It is approximately 400ns/cycle.
I think this timing is too long.
Because I think the read cycle timing can be calculated roughly as the below.
GPMC_FCLK * READCYCLE TIME = 6.02 x 28 = 168.56ns
The result of the measurement shows it is 400ns. It is over twice than register setting value.
What is the wrong?
Please give me advise what should I check.
I appreciate your quick reply.
Best regards,
Michi