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AM335x+TPS65217 Smartreflex-Issue at SDK6

Matthias Walzer
Prodigy 185 points
Other Parts Discussed in Thread: DM3730

I am working on a custom board similar to the BeagleBoneBlack (regarding the PMIC), as there is a AM3354BZCZ100 and a TPS65217D used. I am using the SDK6 to build my kernel.

I am facing weird behaviour of the smartreflex module, as in some cases it never stops setting new voltage, although proper voltage seems to be reached - see the dmesg output below (when running at 1GHz):

[   42.656036] SR 1: curr=1300000, delta_v=-29300, calc=1270700, act=1275000, gain=32
[   43.917846] SR 1: curr=1275000, delta_v=19500, calc=1294500, act=1300000, gain=32
[   45.176025] SR 1: curr=1300000, delta_v=-29300, calc=1270700, act=1275000, gain=32
[   46.436004] SR 1: curr=1275000, delta_v=19500, calc=1294500, act=1300000, gain=32
[   47.697845] SR 1: curr=1300000, delta_v=-29300, calc=1270700, act=1275000, gain=32
[   48.956085] SR 1: curr=1275000, delta_v=19500, calc=1294500, act=1300000, gain=32

The output above was verified by measuring the according voltage: every second it changes between 1.3V and 1.275V.

When sitching to 800MHz via /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed the output is:

[  323.997375] am33xx_sr_cpufreq_transition: prechange
[  323.997497] am33xx_sr_cpufreq_transition: postchange
[  323.997497] am33xx_sr_cpufreq_transition: postchange, new opp=3
[  324.247467] SR 1: curr=1275000, delta_v=-63750, calc=1211250, act=1225000, gain=00
[  325.506103] SR 1: curr=1225000, delta_v=-104150, calc=1120850, act=1125000, gain=29

Then regulation stops, so this is working.

When sitching to 720MHz via /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed the output is:

[  374.328063] am33xx_sr_cpufreq_transition: prechange
[  374.328186] am33xx_sr_cpufreq_transition: postchange
[  374.328186] am33xx_sr_cpufreq_transition: postchange, new opp=2
[  374.587463] SR 1: curr=1200000, delta_v=-60000, calc=1140000, act=1150000, gain=00
[  375.846130] SR 1: curr=1150000, delta_v=-99990, calc=1050010, act=1075000, gain=21
[  377.107971] SR 1: curr=1075000, delta_v=-45144, calc=1029856, act=1050000, gain=21
[  378.376129] SR 1: curr=1050000, delta_v=6435, calc=1056435, act=1075000, gain=21
[  379.637908] SR 1: curr=1075000, delta_v=-38676, calc=1036324, act=1050000, gain=21

In this case again the regulation never stops.

As I am using the TPS65217D I set "vstep_size_uv = 25000" in my am33xx_sr_platform_data.

I am wondering if I am the only one facing this problem - or maybe there is a patch I am not aware of?

I really want to use smartreflex to gain lower power consumption, but the behaviour of that voltage-setting-algorithm seems like beeing not working properly (and it causes unneccessary CPU- and I2C-load)!

  • 0
    TI__Guru**** 393215 points

    Hi Matthias,

    Have you checked if you see the same behavior with SDK 7.0?

  • 0 in reply to Biser Gatchev-XID
    Prodigy 185 points

    No, I did not. Once I tried to migrate to SDK7, but the structure of the SDK is very different from the SDK6, so that I was not able to easily do so....

    I was hoping to still get some support for the SDK6 (as it was a popular one) ....

  • 0 in reply to Matthias Walzer
    TI__Guru**** 393215 points

    I have forwarded this to the SW people.

  • 0 in reply to Biser Gatchev-XID
    TI__Expert 4475 points

    Hi,

    I found 4 patches for SR applied in SDK6:
    0001-am33xx-Add-SmartReflex-support.patch
    0001-Smartreflex-support-for-ES-2.x-and-suspend-resume.patch
    0002-am33xx-Enable-CONFIG_AM33XX_SMARTREFLEX.patch
    0002-Smartreflex-limited-to-ES-1.0.patch

    Did you apply them?

    BR
    Ivan

  • 0 in reply to Ivan Matrakov
    Prodigy 185 points

    Hi Ivan

    As far as I can see all those patches ARE ALREADY applied in SDK6.

    I did never apply them, but the files (am33xx-smartreflex-class2.c, devices.c, board-am335xevm.c and smartreflex.h) in SDK6 show me that those changes are included.

    So, to answer your question: YES, those changes ARE applied!

  • 0 in reply to Matthias Walzer
    TI__Guru*** 125430 points

    This might be indicative of a power issue on your board.  I recommend reviewing this app note on Power Delivery Networks (PDN) that was originally written for DM3730:

    http://www.ti.com/lit/pdf/sprabj7

    The result of your investigation may be as simple as adjusting capacitor values or more complicated like changing your layout.  Have you followed the recommendations from Section 5.9 "External Capacitors" in the AM335x data manual?  Are you using same/similar decoupling as on the BeagleBone Black?

    Brad

  • 0 in reply to Brad Griffis
    Prodigy 185 points

    Hi Brad

    As far as I can see the design is the SAME as on BeagleboardBlack. An 8-plane multilayer PCB was used to avoid decoupling problems. Most of the decoupling capacitors are placed directly "under" the processor (at the opposite side of the PCB) to keep tracelength to a minimum.

    However, it could be a power issue - I can not prove that it is not.

    Are there any descriptions on how the smartreflex-hardware works and interacts with the software? I really want to investigate why the system does not become stable and always tries to set new supplyvoltages!

  • 0 in reply to Matthias Walzer
    TI__Guru*** 125430 points

    Matthias Walzer said:
    As far as I can see the design is the SAME as on BeagleboardBlack. An 8-plane multilayer PCB was used to avoid decoupling problems

    When you say it is the same, do you mean that you are literally using the design files from the BBB to produce your board?  Or do you just mean it's very similar, i.e. same stackup?

    Matthias Walzer said:
    Most of the decoupling capacitors are placed directly "under" the processor (at the opposite side of the PCB) to keep tracelength to a minimum.

    Can you specify what you're using for decoupling caps for MPU and CORE?

    Matthias Walzer said:
    Are there any descriptions on how the smartreflex-hardware works and interacts with the software? I really want to investigate why the system does not become stable and always tries to set new supplyvoltages!

    Mainly due to the fact that we don't want competitors copying this capability, there's not much available describing how it all works.  Sorry, that's clearly not helpful here!  Is your system battery powered, i.e. is the extra power savings from Smart Reflex important to your system?  Another option might be to simply disable it.  I'd recommend a thorough look at PDN first though to make sure we're not just turning a blind eye to a hardware issue.

    FYI, this capability is not present in SDK 7.00, so if you make that migration you will not have this capability at all.

  • 0 in reply to Brad Griffis
    Prodigy 185 points

    Brad Griffis said:
    When you say it is the same, do you mean that you are literally using the design files from the BBB to produce your board?  Or do you just mean it's very similar, i.e. same stackup?

    Sorry for beeing not precise - with design I meant the schematics. The PCB is possibly not even similar, as it is bigger than BBB and the PMIC is about 40mm away from the CPU!

    Brad Griffis said:
    Can you specify what you're using for decoupling caps for MPU and CORE?

    MPU: 1x 10uF/10V/0805/X7R/10%, 3x 100nF/25V/0402/X7R/20%

    CORE: 2x 10uF/10V/0805/X7R/10%, 11x 100nF/25V/0402/X7R/20% (Just realised that these are not as much caps as on BBB - but the problem with smartreflex is located at MPU)!


    One further issue I had to realise is that the feedback of VCORE and VMPU is done directly at the PMIC, not as suggested (by the PDN you mentioned) by a seperate wire from where it is used (at the CPU). However, the static voltage drop there is only 3mV...

  • 0 in reply to Matthias Walzer
    TI__Guru*** 125430 points

    Matthias Walzer said:

    MPU: 1x 10uF/10V/0805/X7R/10%, 3x 100nF/25V/0402/X7R/20%

    CORE: 2x 10uF/10V/0805/X7R/10%, 11x 100nF/25V/0402/X7R/20% (Just realised that these are not as much caps as on BBB - but the problem with smartreflex is located at MPU)!

    Section 5.9.1 "Voltage Decoupling Capacitors" of the data manual specifies:

    • VDD_CORE: 1 x 10uF and 8 x 10nF
    • VDD_MPU: 1 x 10uF and 5 x 10nF

    It might be worth experimenting with some different configurations to see if it has any impact.  For example, what if you replace your 100nF caps on the MPU rail with 10nF caps?  How about stacking them two high (i.e. to give you 6 x 10nF)?

    Matthias Walzer said:
    One further issue I had to realise is that the feedback of VCORE and VMPU is done directly at the PMIC, not as suggested (by the PDN you mentioned) by a seperate wire from where it is used (at the CPU). However, the static voltage drop there is only 3mV...

    I believe this can be PMIC-specific as to the preferred power supply topology.  I recommend sticking with the layout as given in the PMIC data manual.  Some PMICs are designed to have a "remote sense" and others are not.