Hello,
Im trying to get the other UARTs on a BBB to work. The UART0 works correctly. I used uartEcho as a baseline and that worked well for UART0. From there I've worked my way straight to the UART2 which doesnt give any output to the pin, but appears to be correct.
Heres the code responsobile for setting up the UART2:
#include <xdc/std.h>
#include <xdc/runtime/Log.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Semaphore.h>
#include <xdc/cfg/global.h>
#include <stdio.h>
#include "gpio_v2.h"
#include "soc_AM335x.h"
#include "hw_control_AM335x.h"
#include "soc_AM335x.h"
#include "hw_cm_wkup.h"
#include "hw_cm_per.h"
#include "beaglebone.h"
#include "hw_types.h"
#include "interrupt.h"
#include "uart_console.h"
#include "uart_irda_cir.h"
#include <xdc/std.h>
#include <xdc/runtime/System.h>
#include <xdc/runtime/Error.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/family/arm/a8/intcps/Hwi.h>
#include "soc_AM335x.h"
#include "uart_irda_cir.h"
#include "interrupt.h"
#include "hw_cm_wkup.h"
#include "hw_types.h"
#include "hw_control_AM335x.h"
#include "drivers/uart2.h"
Hwi_Handle uart2HwiHandle = NULL;
Void UART2Isr(UArg arg) {
// dumb action (isr shouldn't be empty)
unsigned int i = 0;
}
void UART2Init() {
UART2ClocksSetup(); //long function, moved to the end of this snippet for clarity - but I do believe it is the cause.
HWREG(SOC_CM_PER_REGS + CM_PER_UART2_CLKCTRL) |= CM_PER_UART2_CLKCTRL_MODULEMODE_ENABLE;
while (CM_PER_UART2_CLKCTRL_MODULEMODE_ENABLE !=
(HWREG(SOC_CM_PER_REGS + CM_PER_UART2_CLKCTRL) &
CM_PER_UART2_CLKCTRL_MODULEMODE));
while (CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK));
while ((CM_PER_UART2_CLKCTRL_IDLEST_FUNC << CM_PER_UART2_CLKCTRL_IDLEST_SHIFT) !=
(HWREG(SOC_CM_PER_REGS + CM_PER_UART2_CLKCTRL) &
CM_PER_UART2_CLKCTRL_IDLEST));
/* Pinumx */
//pin muxing takes place right after the device is turned on. Created with pin mux utility, these two lines are responsible for the muxing of UART2
// MUX_VAL(CONTROL_PADCONF_MII1_TX_CLK, (IEN | PD | MODE1 )) ;
// MUX_VAL(CONTROL_PADCONF_MII1_RX_CLK, (IEN | PD | MODE1 )) ;
/* Perform a module reset. */
UARTModuleReset(SOC_UART_2_REGS);
/* Perform FIFO configurations. */
UARTFIFOConfig(SOC_UART_2_REGS,
UART_FIFO_CONFIG(UART_TRIG_LVL_GRANULARITY_1,
UART_TRIG_LVL_GRANULARITY_1, 1, 1, 1, 1,
UART_DMA_EN_PATH_SCR,
UART_DMA_MODE_0_ENABLE));
/* Switch to Configuration Mode B. */
UARTRegConfigModeEnable(SOC_UART_2_REGS, UART_REG_CONFIG_MODE_B);
/* Computing the Divisor Value. */
unsigned int divisor = UARTDivisorValCompute(UART_MODULE_INPUT_CLK,
BAUD_RATE_115200,
UART16x_OPER_MODE,
UART_MIR_OVERSAMPLING_RATE_42);
/* Divisor Latches. */
UARTDivisorLatchWrite(SOC_UART_2_REGS, divisor);
/* Line Characteristics. */
UARTLineCharacConfig(SOC_UART_2_REGS,
(UART_FRAME_WORD_LENGTH_8 | UART_FRAME_NUM_STB_1),
UART_PARITY_NONE);
/* Disable write access to Divisor Latches. */
UARTDivisorLatchDisable(SOC_UART_2_REGS);
/* Disable Break Control. */
UARTBreakCtl(SOC_UART_2_REGS, UART_BREAK_COND_DISABLE);
/* Switch to UART16x operating mode. */
UARTOperatingModeSelect(SOC_UART_2_REGS, UART16x_OPER_MODE);
}
Bool Uart2Open() {
//this creates interrupts and services the tast.
Hwi_Params hwi2Params;
Error_Block eb2;
int intNum2;
if(uart2HwiHandle !=NULL)
return FALSE;
Hwi_Params_init(&hwi2Params);
Error_init(&eb2);
hwi2Params.arg = 1;
hwi2Params.priority = 20;
intNum2 = 74; //UART2Int UART2INT
uart2HwiHandle = Hwi_create(intNum2 , UART2Isr , &hwi2Params, &eb2);
if (Error_check(&eb2)) {
uart2HwiHandle = NULL;
return FALSE;
}
Hwi_enableInterrupt(intNum2);
return TRUE;
}
void UART2PutChar(Char txChar) {
UARTCharPut(SOC_UART_2_REGS, txChar);
}
void UART2PutText(Char *text)
{
while(*text)
UART2PutChar(*(text++));
}
signed char UART2GetChar() {
return (UARTCharGet(SOC_UART_2_REGS));
}
void UART2ClocksSetup() {
/* Configuring L3 Interface Clocks. */
#define CM_PER_L4LS_INSTR_CLKCTRL_MODULEMODE_ENABLE 0x2
#define CM_PER_L4LS_INSTR_CLKCTRL_MODULEMODE 0x3
/* Writing to MODULEMODE field of CM_PER_L4LS_CLKCTRL register. */
HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) |=
CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE;
/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) &
CM_PER_L4LS_CLKCTRL_MODULEMODE));
/* Writing to MODULEMODE field of CM_PER_L4LS_INSTR_CLKCTRL register. */
HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) |=
CM_PER_L4LS_INSTR_CLKCTRL_MODULEMODE_ENABLE;
/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_PER_L4LS_INSTR_CLKCTRL_MODULEMODE_ENABLE !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
CM_PER_L4LS_INSTR_CLKCTRL_MODULEMODE));
/* Writing to CLKTRCTRL field of CM_PER_L4LS_CLKSTCTRL register. */
HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) |=
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
/* Waiting for CLKTRCTRL field to reflect the written value. */
while(CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL));
/* Writing to CLKTRCTRL field of CM_PER_OCPWP_L3_CLKSTCTRL register. */
HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) |=
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
/*Waiting for CLKTRCTRL field to reflect the written value. */
while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
(HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL));
/* Writing to CLKTRCTRL field of CM_PER_L4LSS_CLKSTCTRL register. */
HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) |=
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
/*Waiting for CLKTRCTRL field to reflect the written value. */
while(CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL));
/* Checking fields for necessary values. */
/* Waiting for IDLEST field in CM_PER_L4LS_CLKCTRL register to be set to 0x0. */
while((CM_PER_L4LS_CLKCTRL_IDLEST_FUNC << CM_PER_L4LS_CLKCTRL_IDLEST_SHIFT)!=
(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) &
CM_PER_L4LS_CLKCTRL_IDLEST));
/*
** Waiting for IDLEST field in CM_PER_L4LS_INSTR_CLKCTRL register to attain the
** desired value.
*/
while((CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC <<
CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT)!=
(HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
CM_PER_L3_INSTR_CLKCTRL_IDLEST));
/*
** Waiting for CLKACTIVITY_L3_GCLK field in CM_PER_L4LS_CLKSTCTRL register to
** attain the desired value.
*/
while(CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));
/*
** Waiting for CLKACTIVITY_OCPWP_L3_GCLK field in CM_PER_OCPWP_L3_CLKSTCTRL
** register to attain the desired value.
*/
while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK !=
(HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK));
/*
** Waiting for CLKACTIVITY_L3S_GCLK field in CM_PER_L4LSS_CLKSTCTRL register
** to attain the desired value.
*/
// while(CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK !=
// (HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
// CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));
/* Configuring registers related to Wake-Up region. */
/* Writing to MODULEMODE field of CM_WKUP_CONTROL_CLKCTRL register. */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) |=
CM_WKUP_CONTROL_CLKCTRL_MODULEMODE_ENABLE;
/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_WKUP_CONTROL_CLKCTRL_MODULEMODE_ENABLE !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) &
CM_WKUP_CONTROL_CLKCTRL_MODULEMODE));
/* Writing to CLKTRCTRL field of CM_PER_L4LSS_CLKSTCTRL register. */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) |=
CM_WKUP_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
/*Waiting for CLKTRCTRL field to reflect the written value. */
while(CM_WKUP_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
CM_WKUP_CLKSTCTRL_CLKTRCTRL));
/* Writing to CLKTRCTRL field of CM_L3_AON_CLKSTCTRL register. */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) |=
CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
/*Waiting for CLKTRCTRL field to reflect the written value. */
while(CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) &
CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL));
/* Writing to MODULEMODE field of CM_WKUP_UART0_CLKCTRL register. */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) |=
CM_WKUP_UART0_CLKCTRL_MODULEMODE_ENABLE;
/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_WKUP_UART0_CLKCTRL_MODULEMODE_ENABLE !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) &
CM_WKUP_UART0_CLKCTRL_MODULEMODE));
/* Verifying if the other bits are set to required settings. */
/*
** Waiting for IDLEST field in CM_WKUP_CONTROL_CLKCTRL register to attain
** desired value.
*/
while((CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT) !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) &
CM_WKUP_CONTROL_CLKCTRL_IDLEST));
/*
** Waiting for CLKACTIVITY_L3_AON_GCLK field in CM_L3_AON_CLKSTCTRL
** register to attain desired value.
*/
while(CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) &
CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK));
/*
** Waiting for IDLEST field in CM_WKUP_L4WKUP_CLKCTRL register to attain
** desired value.
*/
while((CM_WKUP_L4WKUP_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_L4WKUP_CLKCTRL_IDLEST_SHIFT) !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_L4WKUP_CLKCTRL) &
CM_WKUP_L4WKUP_CLKCTRL_IDLEST));
/*
** Waiting for CLKACTIVITY_L4_WKUP_GCLK field in CM_WKUP_CLKSTCTRL register
** to attain desired value.
*/
while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK));
/*
** Waiting for CLKACTIVITY_L4_WKUP_AON_GCLK field in CM_L4_WKUP_AON_CLKSTCTRL
** register to attain desired value.
*/
while(CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL) &
CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK));
/*
** Waiting for CLKACTIVITY_UART0_GFCLK field in CM_WKUP_CLKSTCTRL
** register to attain desired value.
*/
while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_UART0_GFCLK !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
CM_WKUP_CLKSTCTRL_CLKACTIVITY_UART0_GFCLK));
/*
** Waiting for IDLEST field in CM_WKUP_UART0_CLKCTRL register to attain
** desired value.
*/
while((CM_WKUP_UART0_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_UART0_CLKCTRL_IDLEST_SHIFT) !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) &
CM_WKUP_UART0_CLKCTRL_IDLEST));
}
