What is the relationship between the display PLL frequency (set via conf_disp_pll in the board file) and the .pxl_clk member of the da8xx_panel struct in the da8xx display driver? I was assuming the pxl_clk member is meant to represent MHz output of the pixel clock.
How do I calculate the display PLL and .pxl_clk value in order to give a desired pixel clock output frequency? Also, if I have multiple displays (multiple structure entries) how do I make sure the PLL value I choose will support different pxl_clk values? Or do I always need to change PLL for different pixel clock frequencies?