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Ethernet over AM437x

M Vismer
Prodigy 60 points
Other Parts Discussed in Thread: SYSBIOS

Hi,

Has anyone managed to get the MII interface ( on port 1) or RGMII on port 2 to work? I think i have made the correct changes to am437x_sysbios_ind_sdk_2.0.0.2\sdk\starterware\examples\enet\tcpecho but have not had any success. 

Does anyone have any sample code? it would be useful to rule out HW/SW issues.

Thanks for any help.

Cheers

Mark

  • 0
    TI__Mastermind 43121 points

    Mark,

    what board are you using for test?

    Regards,

  • 0 in reply to Frank Walzer
    Prodigy 60 points

    Hi Frank,

    Thank you for your prompt response!

    We are using our own custom board with an MII interface on CPSW port 1 and a RGMII interface on port 2.

    I have the sample application working on the IDK EVM AMX43xx board without problems as far as I can tell.

    On our board, the RGMII interface on port 2 appears to work actually (it's just receiving which is a problem and I think this may be due to incorrect clk delays on the RX lines.

    The MII interface on port 1 appears to be wired correctly - I am seeing the ROM bootp packets, but I seem to be having no success when I run the sample with macType set to ETHERNET_MAC_TYPE_MII in enet_phy_device.c (isGigCapab is set to FALSE as well)

    Kind regards
    Mark

  • 0 in reply to M Vismer
    TI__Mastermind 43121 points

    Mark,

    I don't have access to any AM437x board which uses CPSW with MII. Not even sure if this exists at TI.

    So I can't help and you are probably down to standard debug.

    Regards,

  • 0 in reply to M Vismer
    Prodigy 70 points
    Hi Mark,

    Have you ensured the MII pins are configured correctly? In the current version of the AM437x pinmux tool (v3), the code generated does not correctly configure the RXD0 input on MII1. It should have the RX_ENABLE bit set. I have posted a bug report for this here - e2e.ti.com/.../397234.

    Best regards
    Ricardo
  • 0 in reply to Frank Walzer
    Intellectual 585 points
    HI Frank

    I am in a design team working on AM437x processor. We are using RGMII and MII ethernet interface of MAC and PRUICSS subsystem of AM437x.
    I have a below query on Board layout for ethernet interface. I request you to clarify.

    Do we need to add the pcb delay for the RGMII txclock?or else the Processor supports internal delay mode(RGMII_ID) for this?.If internal delay mode supported we need not support the pcb delays.Please confirm.This input is very much required for us.

    Also I found that in both reference evm board files the pcb delay is not supported.

    Let me know for any input from my side.

    Regards
    B. Eshak
  • 0 in reply to Eshak B
    TI__Guru 68880 points
    Eshak, AM437x supports internal TX Delay mode for RGMII. Refer to register CTRL_GMII_SEL.

    Regards,
    James
  • 0 in reply to JJD
    Intellectual 585 points

    Dear JJD

    Thanks for the reply.

    Please clarify my below queries:

    1. Whether the TX delay mode setting is used only in booting time. During normal interface the whether the TX delay mode is possible for RGMII interface?

    2. Whether the time delay setting time can be varied?

    Regards

    B. Eshak

  • 0 in reply to Eshak B
    TI__Guru 68880 points
    Eshak, the TX delay mode can be enabled for booting or during normal operation. There is no adjustment in the time delay setting.

    Regards,
    James
  • 0 in reply to JJD
    Intellectual 905 points
    Hi James,

    I'm in a software design team working on AM437x processor. I'm working on PRU-ICSS MII_RT module.
    I want to forward my PRU-ICSS MII ethernet received packets to GMAC and transmit it through RGMII 1 of GMAC.
    I understood this can be done through L3 and L4 interconnections.
    While checking for this L3 configuration L3F_CFG register details are missing in reference manual.

    Can you please clarify what I understood is correct.
    Can you provide me more information regarding how to achieve this.

    Regards,
    Nithin