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the ddr3 read/write error

hi all

    when i write a 32-bit data and then read it,the lower 16-bit of data is a radom data(the high 16bit is correct).

The board is my custom,the DDR PLL CLOCKOUT is on 400MHz.the sdram chip is MT-ddr3-1600.

I check my emif4d register accoring to the sdram-datasheet timing parameters.and config the PHY register following the TI's wiki,

but the scene still exists.

Is there some register about this,like the burst operation?

thanks advnce.

  • Hi,

    What processor are you using?

  • hi biser
    I follow the link you provide.In my custom board the sdram chip part-number is almost same as the example used.the difference between my board and the example is the ddr_ck/ddr_dqs trace length.

    The sdram-chip is 16-bit width.
    Is the DDR-PHY timing not configured correctly?
    because the upper 16 bit data is writed and read correct.the lower 16-bit is not in the dqs/dqsn timing windows?
  • This tuning needs to be done once only for each new PCB design.

  • I did the tuning for my custom board,using the ddr_ck/ddr_dqs trace length on my board.
  • And everything came out OK? Then there must be a hardware (maybe schematic???) error.

  • What software/version are you using?

  • software version?is it the ddr3 software leveling?

    hardware error?but the upper 16-bit is correct,the sdram-chip is 16-bit.

    I will check the schematic.

  • It almost seems like you have the controller setup in 32-bit mode or something is different in your SDRAM_CONFIG register. What is the value of this reg? What is the memory part number?

    James
  • hi james

    the sdram-chip part number is:MT41J256M16RE-125;

    In my design SDRAM_CONFIG:(0x61C45332)

  • Can you run the script documented here and attach the resulting output:

  • hi I will tell the hardware to do the simulate.but I think the hardware is ok.
    now I use the BeagleBlack_400Mhz_4GbDDR.gel to initialise my board and do the "data_transfercheck"
    DDR_START_ADDR:0x80000000;
    temp_reg_wr = 0xA5B6C7D8;
    NO_LOOP_CNT:256;
    the read and write are all ok.

    But when uart boot mode I use the same emif and dd-phy config register to do the same thing ;
    the read back data will be changed,as bellow:
    Try Accessing DDR memory address:0x80000000 ....Read data:0xC7D8D5F6

    Try Accessing DDR memory address:0x80000004 ....Read data:0xC7D8A5B6

    Try Accessing DDR memory address:0x80000008 ....Read data:0xC7D8A5B6

    Try Accessing DDR memory address:0x8000000C ....Read data:0xC7D8A5B6

    Try Accessing DDR memory address:0x80000010 ....Read data:0xC7D8DE74

    Try Accessing DDR memory address:0x80000014 ....Read data:0xC7D8A5B6

    Try Accessing DDR memory address:0x80000018 ....Read data:0xC7D8A5B6

    Try Accessing DDR memory address:0x8000001C ....Read data:0xC7D8A5B6

    Try Accessing DDR memory address:0x80000020 ....Read data:0xC7D8ED23

    Try Accessing DDR memory address:0x80000024 ....Read data:0xC7D8A5B6

    Try Accessing DDR memory address:0x80000028 ....Read data:0xC7D8A5B6

    Try Accessing DDR memory address:0x8000002C ....Read data:0xC7D8A5B6

    Try Accessing DDR memory address:0x80000030 ....Read data:0xC7D89FDC
    ..............................
    I check my schematic the dq[0:15] is connected correct.
  • I use the same emif and ddr-phy configuration to run the "DDR_DataTransferCheck"code use the jatg and uart-mode ,jatg is ok,but uart-mode is failed.
    and I run the "DDR_DataTransferCheck"using the different emif and ddr-phy configuration on other manufacture am3358-board,it is ok.
    can anybody help me!
  • I would perform a data dump of the EMIF registers between the JTAG init and the UART init to see if there are any differences. The registers you should be comparing are:

    EMIF: 0x4c000000-0x4c000120

    regards,
    James
  • hi JJD
    thx for your suggestion.
    I dump the emif registers between the jatg init and uart init but they seem almost same,except a few read-only register like EMIF_PERF_CNT_TIM_REG.
    It seems like a hardware error,but the jatg is ok!
    I was bothered by this problem.
  • jatg_info.txt
    CortxA8: Output: -------------------EMIF register data dump ....... 
    ---EMIF_STATUS_REG :: 0x40000004 
    ---EMIF_SDRAM_CONFIG_REG :: 0x61C05332 
    ---EMIF_SDRAM_CONFIG_2_REG :: 0x00000000 
    ---EMIF_SDRAM_REF_CTRL_REG :: 0x00000C30 
    ---EMIF_SDRAM_REF_CTRL_SHDW_REG :: 0x00000C30 
    ---EMIF_SDRAM_TIM_1_REG :: 0x0AAAD4DB 
    ---EMIF_SDRAM_TIM_1_SHDW_REG :: 0x0AAAD4DB 
    ---EMIF_SDRAM_TIM_2_REG :: 0x266B7FDA 
    ---EMIF_SDRAM_TIM_2_SHDW_REG :: 0x266B7FDA 
    ---EMIF_SDRAM_TIM_3_REG :: 0x501F867F 
    ---EMIF_SDRAM_TIM_3_SHDW_REG :: 0x501F867F 
    ---EMIF_LPDDR2_NVM_TIM_REG :: 0x00000000 
    ---EMIF_LPDDR2_NVM_TIM_SHDW_REG :: 0x00000000 
    ---EMIF_PWR_MGMT_CTRL_REG :: 0x00000000 
    ---EMIF_PWR_MGMT_CTRL_SHDW_REG :: 0x00000000 
    ---EMIF_LPDDR2_MODE_REG_DATA_REG :: 0x00000000 
    ---EMIF_LPDDR2_MODE_REG_CFG_REG :: 0x00000000 
    ---EMIF_OCP_CONFIG_REG :: 0x00FFFFFF 
    ---EMIF_OCP_CFG_VAL_1_REG :: 0x8000140A 
    ---EMIF_OCP_CFG_VAL_2_REG :: 0x00021616 
    ---EMIF_IODFT_TLGC_REG :: 0x00002011 
    ---EMIF_IODFT_CTRL_MISR_RSLT_REG :: 0x00000000 
    ---EMIF_IODFT_ADDR_MISR_RSLT_REG :: 0x00000000 
    ---EMIF_IODFT_DATA_MISR_RSLT_1_REG :: 0x00000000 
    ---EMIF_IODFT_DATA_MISR_RSLT_2_REG :: 0x00000000 
    ---EMIF_IODFT_DATA_MISR_RSLT_3_REG :: 0x00000000 
    ---EMIF_PERF_CNT_1_REG :: 0x00000000 
    ---EMIF_PERF_CNT_2_REG :: 0x00000000 
    ---EMIF_PERF_CNT_CFG_REG :: 0x00010000 
    ---EMIF_PERF_CNT_SEL_REG :: 0x00000000 
    ---EMIF_PERF_CNT_TIM_REG :: 0x1347FFBE 
    ---EMIF_READ_IDLE_CTRL_REG :: 0x00050000 
    ---EMIF_READ_IDLE_CTRL_SHDW_REG :: 0x00050000 
    ---EMIF_IRQ_EOI_REG :: 0x00000000 
    ---EMIF_IRQSTATUS_RAW_SYS_REG :: 0x00000000 
    ---EMIF_IRQSTATUS_SYS_REG :: 0x00000000 
    ---EMIF_IRQSTATUS_LL_REG :: 0x00000000 
    ---EMIF_IRQENABLE_SET_SYS_REG :: 0x00000000 
    ---EMIF_IRQENABLE_SET_LL_REG :: 0x00000000 
    ---EMIF_IRQENABLE_CLR_SYS_REG :: 0x00000000 
    ---EMIF_ZQ_CONFIG_REG :: 0x50074BE4 
    ---EMIF_TEMP_ALERT_CONFIG_REG :: 0x00000000 
    ---EMIF_OCP_ERR_LOG_REG :: 0x00000000 
    ---EMIF_RDWR_LVL_RMP_WIN_REG :: 0x00000000 
    ---EMIF_RDWR_LVL_RMP_CTRL_REG :: 0x00000000 
    ---EMIF_RDWR_LVL_CTRL_REG :: 0x00000000 
    ---EMIF_DDR_PHY_CTRL_1_REG :: 0x00000007 
    ---EMIF_DDR_PHY_CTRL_1_SHDW_REG :: 0x00000007 
    ---EMIF_DDR_PHY_CTRL_2_REG :: 0x00000007 
    ---EMIF_PRI_COS_MAP_REG :: 0x00000000 
    ---EMIF_CONNID_COS_1_MAP_REG :: 0x00000000 
    ---EMIF_CONNID_COS_2_MAP_REG :: 0x00000000 
    ---EMIF_RD_WR_EXEC_THRSH_REG :: 0x00000305 
    CortxA8: Output: -------------------EMIF register data dump completed.......
    uart_info.txt
    d-------------------EMIF register data dump ....... 
    
     ---EMIF_STATUS_REG :: 0x40000004
     ---EMIF_SDRAM_CONFIG :: 0x61C05332
     ---EMIF_SDRAM_CONFIG_2 :: 0x0
     ---EMIF_SDRAM_REF_CTRL :: 0xC30
     ---EMIF_SDRAM_REF_CTRL_SHDW :: 0xC30
     ---EMIF_SDRAM_TIM_1 :: 0xAAAD4DB
     ---EMIF_SDRAM_TIM_1_SHDW :: 0xAAAD4DB
     ---EMIF_SDRAM_TIM_2 :: 0x266B7FDA
     ---EMIF_SDRAM_TIM_2_SHDW :: 0x266B7FDA
     ---EMIF_SDRAM_TIM_3 :: 0x501F867F
     ---EMIF_SDRAM_TIM_3_SHDW :: 0x501F867F
     ---EMIF_LPDDR_NVM_TIM2 :: 0x0
     ---EMIF_LPDDR_NVM_TIM_SHDW2 :: 0x0
     ---EMIF_PWR_MGMT_CTRL :: 0x0
     ---EMIF_PWR_MGMT_CTRL_SHDW :: 0x0
     ---EMIF_LPDDR_MODE_REG_DATA2 :: 0x0
     ---EMIF_LPDDR_MODE_REG_CFG2 :: 0x0
     ---EMIF_L3_CONFIG :: 0xFFFFFF
     ---EMIF_L3_CONFIG_VAL_0 :: 0x8000140A
     ---EMIF_L3_CONFIG_VAL_1 :: 0x21616
     ---EMIF_IODFT_TLGC :: 0x2011
     ---EMIF_IODFT_CTRL_MISR_RSLT :: 0x0
     ---EMIF_IODFT_ADDR_MISR_RSLT :: 0x0
     ---EMIF_IODFT_DATA_MISR_RSLT_0 :: 0x0
     ---EMIF_IODFT_DATA_MISR_RSLT_1 :: 0x0
     ---EMIF_IODFT_DATA_MISR_RSLT_2 :: 0x0
     ---EMIF_PERF_CNT_0 :: 0x0
     ---EMIF_PERF_CNT_1 :: 0x0
     ---EMIF_PERF_CNT_CFG :: 0x10000
     ---EMIF_PERF_CNT_SEL :: 0x0
     ---EMIF_PERF_CNT_TIM :: 0x24DA3F8
     ---EMIF_READ_IDLE_CTRL :: 0x50000
     ---EMIF_READ_IDLE_CTRL_SHDW :: 0x50000
     ---EMIF_IRQ_EOI :: 0x0
     ---EMIF_IRQSTATUS_RAW_SYS :: 0x0
     ---EMIF_IRQSTATUS_RAW_LL :: 0x0
     ---EMIF_IRQSTATUS_SYS :: 0x0
     ---EMIF_IRQSTATUS_LL :: 0x0
     ---EMIF_IRQENABLE_SET_SYS :: 0x0
     ---EMIF_IRQENABLE_SET_LL :: 0x0
     ---EMIF_IRQENABLE_CLR_SYS :: 0x0
     ---EMIF_IRQENABLE_CLR_LL :: 0x0
     ---EMIF_ZQ_CONFIG :: 0x50074BE4
     ---EMIF_TEMP_ALERT_CONFIG :: 0x0
     ---EMIF_L3_ERR_LOG :: 0x0
     ---EMIF_RDWR_LVL_RMP_WIN :: 0x0
     ---EMIF_RDWR_LVL_RMP_CTRL :: 0x0
     ---EMIF_RDWR_LVL_CTRL :: 0x0
     ---EMIF_DDR_PHY_CTRL_1 :: 0x7
     ---EMIF_DDR_PHY_CTRL_1_SHDW :: 0x7
     ---EMIF_DDR_PHY_CTRL_2 :: 0x7
     ---EMIF_PRI_COS_MAP :: 0x0
     ---EMIF_CONNID_COS_1_MAP :: 0x0
     ---EMIF_CONNID_COS_2_MAP :: 0x0
     ---EMIF_RD_WR_EXEC_THRSH :: 0x305
    -------------------EMIF register data dump completed....... 
    two attachement is the printf infos from jatg init and uart init

  • hi all
    can anybody tell me the field "reg_read_latency"in register"DDR_PHY_CTRL_1",it control the delay cycle when PHY to capture the data back from sdram?
    if so,when I change it with CL+2(min) and CL+7(max),the data read from sdram not changed.

    I mean how this field will reflects the emif controller and ddr-phy.
     
    thanks in advance

  • Brad Griffis said:

    Can you run the script documented here and attach the resulting output:

    How to use the AM335x IBIS Models - Texas Instruments Wiki

    processors.wiki.ti.com