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Warm reset problem for AM3517 with TPS65910 during I2C interface

Kzk
Genius 5785 points
Other Parts Discussed in Thread: AM3517, TPS65910

Hello,

I have a system problem regarding I2C interface on my target board after warm reset. AM3517 uses i2c1_scl and i2c1_sda to connect TPS65910. AM3517 reads RTC of PMIC by I2C periodically. AM3517 can't reboot If occurring external warm reset assertion during this I2C access. Because SDA is held low by PMIC and SCL is stopped by AM3517 as I2C master. After that rebooting, AM3517 can't interface to PMIC on I2C and start system.

Is it a specification of AM3517 that SCL stops as soon as warm reset? Can I2C module of AM3517 send some clocks after warm reset? I read following description. But i2c1_scl is not multiplex with GPIO, and I2C module of AM3517 doesn't have a functionality for "free data format". How do I resolve this problem?

processors.wiki.ti.com/.../I2C_Tips

Regards,
Kazu

  • 0
    TI__Guru**** 393215 points

    Hi Kazu-san,

    Warm reset is a global device reset that affects almost the entire processor. There is no way I2C to continue functioning once it's asserted. Maybe a possible solution to your problem could be to have I2C pins double-connected to a couple of GPIOs that will give you the ability to monitor SDA after reset and if necessary inject SCL clocks to bring the bus out of hanging state.

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points

    Hello Biser,

    Thank you for your advice. Do you mean the connection below?

    1) Connect SDA pin of PMIC to i2c1_sda and gpio_xx of AM3517.

    2) Connect SCL pin of PMIC to i2c1_scl and gpio_yy of AM3517.

    gpio_yy sends some pulses if gpio_xx is low level. Is it correct?

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Guru**** 393215 points

    Yes, something like that. Of course care must be taken about pinmuxing the GPIOs correctly, so as not to interfere with I2C, and also choose GPIOs that will not block I2C in their default reset release state.

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points

    Hello Biser,

    Thank you for your quick reply. If possible, I don't want to modify PCB. If AM3517 UART reads data from slave address zero configured I2C_SA register, I think the pulse is similar to "free data format". Actually there is not a device as slave address zero. But I'm anxious about signal collision with PMIC on SDA line. What do you think?

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Guru**** 393215 points

    I'm afraid I don't understand.

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points
    Hello Biser,

    I apologize for any confusion. To release hanging state of PMIC, I understand that I need to send some pulses at SCL from AM3517 to PMIC. And I need to use GPIO to make it realized in your suggestion. But I can't use i2c1_scl as GPIO. So I'd like to send some pulses at SCL without using GPIO.

    If reading operation of I2C is occurred by rebooted AM3517, this will lead with sending some pulse at SCL. I hope it leads to release hanging stat of PMIC. And if slave address by I2C_SA register is zero, it seems that there are low level bits in slave address phase at SDA. Driving low level by PMIC and AM3517 don't have signal collision at SDA, I think. But in this method, I can't recognize whether PMIC is in hanging state or not.

    May I ask if you understand what I mean?

    Regards,
    Kazu
  • 0 in reply to Kzk
    TI__Guru**** 393215 points

    As far as I remember the I2C master must send 9 clock pulses on SCL to reset the slave. What I am not sure of is whether the master will even try to start a read operation if SDA is held low.

    There is a note in Section 15.2.1.3.10 of the AM35X TRM that describes this situation. Maybe the 9 clocks can be implemented via the I2C_SYSTEST register bit SCL_O.

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points
    Hello Biser,
    Thank you for your help. I'll implement using I2C_SYSTEST like below to release I2C bus. I suppose SCL frequency is 100KHz. I will report results. Please let me know if there is any point that you notice about this code. 

    ST_EN = 1; // system test enabled.
    if (SDA_I == 0) {
        // PMIC is hanging.
        for (i = 0; i < 9; i++) {
            SCL_O = 0; wait_micro_second(5);
            if (SDA_I == 1) {
                // make a sequence for a stop condition.
                SDA_O = 0; wait_micro_second(1);
                SCL_O = 1; wait_micro_second(5);
                SDA_O = 1; wait_micro_second(5);
                break;
            }
            SCL_O = 1; wait_micro_second(5);
        }
    }
    ST_EN = 0; // normal mode.

    Regards,
    Kazu
  • 0 in reply to Kzk
    TI__Guru**** 393215 points

    I'm not a SW expert, but should be something like that.

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points

    Hello Biser,

    I appreciate your support. I can send 9 clock pulses on SCL using SCL_O bit of I2C_SYSTEST resister on logicPD AM3517EVM. I also configure this register in order to enter test mode before sending pulses. First I set ST_EN, then set SCL_O and SDA_O, finally I set TMODE as "loop back + SDA/SCL IO mode select". I’m worried about a behavior after this process. I seem that SCL and SDA falls for only a moment after I set TMODE. I see that they are high level before this process, and I set them as high level. Do you know why they fall once? I think their level should be kept high level to begin recovery operation of slave.

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Guru**** 393215 points

    Can you try another sequence instead:

    ST_EN=1

    TMODE=2

    Poll SDA_I until it becomes 1

    TMODE=0

    ST_EN=0

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points

    Hello Biser,

    Thank you for your advice. I don't need to set SCL_O and SDA_O, do I? But SCL falls to a low level before polling SDA level if I don't set SCL_O. Because the initial value of SCL_O is zero(a low level). I don't want to send SCL as a low level when SDA level is high which means PMIC is not hang-up. Do you have any suggestion?

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Guru**** 393215 points

    Well, then perhaps the very first step should be to check SDA_I and if it's high just skip the whole procedure.

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points

    Hello Biser,

    I configure and read registers to check SDA level.

    ST_EN=1

    TMODE=2

    -> Regardless of SDA level, SCL is falling at this timing.

    Poll SDA_I until it becomes 1

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Guru**** 393215 points

    What I mean is that you try to check if SDA_I=1 before ST_EN=1.

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points

    Hello Biser,

    SDA signal doesn't propagate internally from SDA pin to SDA_I bit without setting TMODE to SDA/SCL I/O mode. And also, TMODE isn't enabled without setting ST_EN. The result is the same even if I set ST_EN, TMODE, SDA_O and SCL_O at a time. The level of SDA and SCL is low for 200 nano second. The level ramps up slowly, then comes up to high after 1 micro second. Could you give me some advice?

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Guru**** 393215 points

    I see. I was hoping that SDA_I can be read without switching to test mode, but it seems this is not possible. I don't see anything that can be done to avoid this drop on I2C lines when switching to test mode.

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points

    Hello Biser,

    I see, thank you anyway. I think the drop is not caused a condition of start bit, so I hope PMIC will ignore the drop. I think this check method is applicable to release PMIC, so we're going to test on the target board. I appreciate your help.

    Regards,
    Kazu