Custom AM335X with Marvell's 88E1510 RGMII Ethernet Gigabit PHY

Waman

Hello:

I 've a Custom AM335X board with Marvell's 88E1510 RGMII Ethernet Gigabit PHY and I'm not able make the Internet working.

Below is the code snippet used in linux/arch/arm/mach-omap2/board.c

/* Marvell GigaBit PHY 88E1510 */
#define MARVELL_88E15xx 0x1410dd1
#define MARVELL_MII_PAGE2_MAC_CONTROL 21
#define MARVELL_MII_PAGE_ADDRESS 22

#include <linux/marvell_phy.h>

static int marvell_phy_fixup(struct phy_device *phydev)
{
   /* This disables internally transmit clock delay */
   unsigned int val;
   int timeout;
   phy_write(phydev, MARVELL_MII_PAGE_ADDRESS, 2); /* select page 2 */
   val = phy_read(phydev, MARVELL_MII_PAGE2_MAC_CONTROL);
   val &= ~0x10; /* RGMII Transmit Timing Control */
   phy_write(phydev, MARVELL_MII_PAGE2_MAC_CONTROL, val);
   phy_write(phydev, MARVELL_MII_PAGE_ADDRESS, 0); /* back to page 0 */
   /* Changes to MAC CONTROL register must be followed by software reset to take effekt */
   val = phy_read(phydev, MII_BMCR);
   val |= BMCR_RESET;
   phy_write(phydev, MII_BMCR, val);
   timeout = 100;
   while (--timeout) {
       if (!(phy_read(phydev, MII_BMCR) & BMCR_RESET))
       break;
       udelay(1);
       }
    if (!timeout)
       printk(KERN_ERR "Marvell phy addr %d BMCR reset failed.\n", phydev->phy_id);

   return 0;
}

static struct pinmux_config mv_phy_pin_mux[] = {
   {"gpmc_a0.rgmii2_tctl",   OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
   {"gpmc_a1.rgmii2_rctl",   OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
   {"gpmc_a2.rgmii2_td3",   OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
   {"gpmc_a3.rgmii2_td2",   OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
   {"gpmc_a4.rgmii2_td1",   OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
   {"gpmc_a5.rgmii2_td0",   OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
   {"gpmc_a6.rgmii2_tclk",   OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
   {"gpmc_a7.rgmii2_rclk",   OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
   {"gpmc_a8.rgmii2_rd3",   OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
   {"gpmc_a9.rgmii2_rd2",   OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
   {"gpmc_a10.rgmii2_rd1",   OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
   {"gpmc_a11.rgmii2_rd0",   OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
   {"mcasp0_aclkr.gpio3_18", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},
   {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
   {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
   {"mii1_col.gpio3_0", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
   {NULL, 0},
};

static void __init mv_phy_init(void)
{
   setup_pin_mux(mv_phy_pin_mux);
   am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, NULL, "0:01");

   /* Marvell Phy fixup */
   phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK,
                   marvell_phy_fixup);
}

On the custom board;

Linux am335x-evm 3.2.0 #106 PREEMPT Wed Feb 11 17:05:13 IST 2015 armv7l GNU/Linux

[ 1.440246] davincimdio davincimdio.0: detected phy mask fffd
[ 1912.335388] net eth1: CPSW phy found : id is : 0x1410dd1
[ 1917.335968] PHY: 0:01 - Link is Up - 1000/Full
[ 1.468994] davincimdio davincimdio.0: phy[1]: device 0:01, driver Marvell 88E1510
[ 2.066650] cpsw: Detected MACID = d0:ff:50:87:d3:5e

udhcpc fails. So I've statically assigned the IP address but ping is not working.

Any kind of support is highly appreciated.

Regards,

Waman Prabhu.

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

Eth1 is not up by default. Have you tried to bring it up manually? See: http://processors.wiki.ti.com/index.php/AM335x_CPSW_(Ethernet)_Driver's_Guide#Bringing_Up_interfaces

0 Waman over 9 years ago in reply to Biser Gatchev-XID

Prodigy 70 points

log.txt

root@am335x-evm:~# cat /sys/devices/platform/omap/cpsw/net/eth1/hw_stats 
CPSW Statistics:
rxcrcerrors .............................       5324
rxaligncodeerrors .......................      12703
rxfragments .............................      21967
txgoodframes ............................         47
txbroadcastframes .......................         47
txoctets ................................      15322
octetframes64 ...........................       3112
octetframes65t127 .......................       7940
octetframes128t255 ......................       6404
octetframes256t511 ......................        552
octetframes512t1023 .....................         62
octetframes1024tup ......................          4
netoctets ...............................    3897328

RX DMA Statistics:
head_enqueue ............................          1
tail_enqueue ............................         63
busy_dequeue ............................         47

TX DMA Statistics:
head_enqueue ............................         47
empty_dequeue ...........................         47
good_dequeue ............................         47
root@am335x-evm:~#


gpmc_a6
root@am335x-evm:~# devmem2 0x44e10858
/dev/mem opened.
Memory mapped at address 0x4010f000.
Read at address  0x44E10858 (0x4010f858): 0x00000002

gpmc_a0
root@am335x-evm:~# devmem2 0x44e10840
/dev/mem opened.
Memory mapped at address 0x4015a000.
Read at address  0x44E10840 (0x4015a840): 0x00000002

cpsw mac clk ctrl
root@am335x-evm:~# devmem2 0x44e00014
/dev/mem opened.
Memory mapped at address 0x4002a000.
Read at address  0x44E00014 (0x4002a014): 0x00000002

cpsw clk cntrl
root@am335x-evm:~# devmem2 0x44e00144
/dev/mem opened.
Memory mapped at address 0x400b8000.
Read at address  0x44E00144 (0x400b8144): 0x00000012

div m5 dpll core
root@am335x-evm:~# devmem2 0x44e00484
/dev/mem opened.
Memory mapped at address 0x4013d000.
Read at address  0x44E00484 (0x4013d484): 0x00000228

Hi Biser,

We have made PHY01 as a default one. eth1 is there once the system is up. I've also tried setting it up manually with no luck.

I'm still not able make the DHCP/ping working.

We are using ti-sdk-am335x-evm-06.00.00.00. We get 25Mhz on Tx clock from the Am335x and 25mhz on the rx clock from the PHY.

We are seeing rxcrcerrors and rxaligncodeerrors. Please see attached a file which has details of the scenario and relevent register values read. or

root@am335x-evm:~# cat /sys/devices/platform/omap/cpsw/net/eth1/hw_stats
CPSW Statistics:
rxcrcerrors .............................       5324
rxaligncodeerrors .......................      12703
rxfragments .............................      21967
txgoodframes ............................         47
txbroadcastframes .......................         47
txoctets ................................      15322
octetframes64 ...........................       3112
octetframes65t127 .......................       7940
octetframes128t255 ......................       6404
octetframes256t511 ......................        552
octetframes512t1023 .....................         62
octetframes1024tup ......................          4
netoctets ...............................    3897328

RX DMA Statistics:
head_enqueue ............................          1
tail_enqueue ............................         63
busy_dequeue ............................         47

TX DMA Statistics:
head_enqueue ............................         47
empty_dequeue ...........................         47
good_dequeue ............................         47
root@am335x-evm:~#

gpmc_a6
root@am335x-evm:~# devmem2 0x44e10858
/dev/mem opened.
Memory mapped at address 0x4010f000.
Read at address 0x44E10858 (0x4010f858): 0x00000002

gpmc_a0
root@am335x-evm:~# devmem2 0x44e10840
/dev/mem opened.
Memory mapped at address 0x4015a000.
Read at address 0x44E10840 (0x4015a840): 0x00000002

cpsw mac clk ctrl
root@am335x-evm:~# devmem2 0x44e00014
/dev/mem opened.
Memory mapped at address 0x4002a000.
Read at address 0x44E00014 (0x4002a014): 0x00000002

cpsw clk cntrl
root@am335x-evm:~# devmem2 0x44e00144
/dev/mem opened.
Memory mapped at address 0x400b8000.
Read at address 0x44E00144 (0x400b8144): 0x00000012

div m5 dpll core
root@am335x-evm:~# devmem2 0x44e00484
/dev/mem opened.
Memory mapped at address 0x4013d000.
Read at address 0x44E00484 (0x4013d484): 0x00000228

Regards,
Waman Prabhu

0 Matthew Schuckmann1 over 8 years ago

Intellectual 975 points

Hi Waman,

Did you ever get you issue resolved?
I'm trying to get an 88E1510 to work in u-boot and I can not get DHCP or ping to work at all.

Thanks,
Matt S.

0 Waman Prabhu over 8 years ago in reply to Matthew Schuckmann1

Prodigy 235 points

Hi Matt,

No I haven't tried making the 88E1510 work in u-boot. However it works fine now in the kernel image.

Thanks,

Waman Prabhu.

0 Matthew Schuckmann1 over 8 years ago in reply to Waman Prabhu

Intellectual 975 points

Waman,

Thanks for the reply, can I ask what you did to get it working in Linux? And or what version of Linux you are using?

Thanks,

Matt S.

0 Waman Prabhu over 8 years ago in reply to Matthew Schuckmann1

Prodigy 235 points

Hi Matt,

Kernel version is 3.2.0

changes made to drivers/net/phy/marvell.c are as follows;

diff --git a/linux/drivers/net/phy/marvell.c b/linux/drivers/net/phy/marvell.c
index 8e8de42..820cfd8 100755
--- a/linux/drivers/net/phy/marvell.c
+++ b/linux/drivers/net/phy/marvell.c
@@ -280,27 +280,38 @@ static int m88e1121_config_aneg(struct phy_device *phydev)
if (err < 0)
return err;

+ phydev->interface = PHY_INTERFACE_MODE_RGMII_TXID;
+
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
-
- mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
- MII_88E1121_PHY_MSCR_DELAY_MASK;
-
+ mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG);// & MII_88E1121_PHY_MSCR_DELAY_MASK;
+ //printk("..1.. mscr %d\n",mscr);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ {
+ //printk("..2..\n");
mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
MII_88E1121_PHY_MSCR_TX_DELAY);
+ //printk("..2.. mscr %d\n",mscr);
+ }
else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ {
+ //printk("..3..\n");
mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
+ }
else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ {
+ //printk("..4..\n");
mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
-
+ }
err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
if (err < 0)
return err;
}
+ //mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG);

+ //printk("..5.. mscr %d\n",mscr);
phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);

err = phy_write(phydev, MII_BMCR, BMCR_RESET);
@@ -319,7 +330,6 @@ static int m88e1121_config_aneg(struct phy_device *phydev)
phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);

err = genphy_config_aneg(phydev);
-
return err;
}

Hope this helps.

Regards,

Waman Prabhu.

0 Waman over 7 years ago in reply to Matthew Schuckmann1

Prodigy 70 points

Hello Matt S

Did you have the DHCP working on u-boot? Any luck on kernel side as well?

Thanks.

Regards,

Waman Prabhu

0 Matthew Schuckmann1 over 7 years ago in reply to Waman

Intellectual 975 points

Yes I did,

I don't have the details available to me now but it was mostly about getting the RX and TX delays set properly. If you are still stuck let me know and I can get you more details.

Matt S.

0 Waman Prabhu over 7 years ago in reply to Matthew Schuckmann1

Prodigy 235 points

Hi Matt,

I need the U-boot code changes for making the DHCP/Ethernet work.

Thanks

Waman Prabhu

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Custom AM335X with Marvell's 88E1510 RGMII Ethernet Gigabit PHY