Hi community member,
Would you please provide advice for the following phenomenon?
[Phenomenon]
The outputted HSYNC and VSYNC clock is twice faster than my customer required.
Now my customer have used the 1600x480 size LCD for their application. And checked the fbset and show it as below.
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mode "1600x480-51"
# D: 41.501 MHz, H: 25.000 kHz, V: 51.021 Hz
geometry 1600 480 1600 480 32
timings 24096 15 15 2 2 30 6
rgba 8/16,8/8,8/0,8/24
endmode
******************************************************
The HSYNC was outputted 50kHz and the VSYNC was outputted 102Hz even though the fbset was set as above.
So, it showed half size on LCD. And they set the DPLL_DISP as below.
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address data
LCD_CTRL 0x4830E004 0x00000202
CM_CLKMODE_DPLL_DISP 0x44E00498 0x00000007
CM_CLKSEL_DPLL_DISP 0x44E00454 0x00002104
CM_DIV_M2 0x44E004A4 0x00000201
CLKSEL_LCDC_PIXEL_CLK 0x44E00534 0x00000000
********************************************************
If you need more information in order to solve this problem, please let me know.
Best regards.
Kaka
