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On AM335x, how to use Register SD_SYSCTL, field CLKD to configure clock frequency for MMC1 (example)

Hello,

I need to know which clock frequencies are available for SDIO function.

I check with spruh73l.pdf (latest Technical Reference Manual). As far as I see the reference frequency is 96MHz from ROM boot, if nothing has changed that.

Based on that, what frequencies are possible?
In the TRM section 18.4.1.18 describes register SD_SYSCTL. In this the Field CLKD is given as bits 15-6, i.e. 6 bits wide.

The description lists the values 0h, 1h, 2h, 3h and 3FFh. It looks like the 96MHz are divided by the value in Field CLKD (with CLKD=0 as 96MHz).
However there is no indication - like an ellipsis ... - indicating the hole sequence from 2h to 3FFh is possible as value.

Is my interpretation correct, to allow for any divider up to 3FFh (1023)?
And reading in post e2e.ti.com/.../378589 , is the reference clock given as 96MHz or 48MHz? I understand the maximum output is 48MHz.

Thanks for clarification

brgds
Wilfried