I found this post that basically describes the exact same problem I'm experiencing, but didn't report how to accomplish the solution. I'm trying to talk to an Ethernet PHY via RGMII from an AM3358, but the RGMII transmit clock is incorrect. At 10MB, it's 1MHz, at 100MB it's 10MHz, and at Gigabit it's 50MHz. Apparently this is controlled by a PLL setting.
Isn't the device tree supposed to take care of this for me? The am33xx.dtsi file includes the following:
mac: ethernet@4a100000 {
compatible = "ti,cpsw";
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
clock-names = "fck", "cpts";
/* ... and more ... */
And I'm not modifying any of that in the device tree file for our board.
What is the proper way to configure the PLL setting?
