AM3359 PHY_INVERT_CLKOUT

Hi,

Yes, you can use PHY_INVERT_CLKOUT = 1. It should work.

Hi Biser-san,

When the conditions of DDR_DQS0 > DDR_CLK and DDR_DQS1 < DDR_CLK, why the same register value can be applied to the DATAx_PHY_RD_DQS_SLAVE_RATIO registers or the DATAx_PHY_WR_DQS_SLAVE_RATIO registers?

Our customer has the board which is the conditions of DDR_DQS0 < DDR_CLK and DDR_DQS1 > DDR_CLK. They worry whether it is correct that the same register value is used for the DQS0 and DQS1.

I guess that the optimum register value for each DQS should be used to provide the biggest margin, but that the same register value can be used if the skew between DQS0 and DQS1 is short enough to have the valid DQS period long enough.

In addition, PHY_INVERT_CLKOUT=1 is needed to get the optimum register values by the software leveling.

Is my guess correct?

Best regards,

Daisuke

The DDR tuning procedures are given in http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips I have no additional information other than what is described there.

Hi Biser-san,

Thank you for your reply.

Can you not ask the design team for additional information?

The customer requires the true optimum register values because their board is used on the medical equipments.

Best regards,

Daisuke

I have the same concern too, is the tuning based on an average of both byte lanes?

Hi Biser-san,

Please make it clear whether the software leveling supports the cases of DDR_DQS0 > DDR_CLK > DDR_DQS1 and DDR_DQS0 < DDR_CLK < DDR_DQS1. If does not support it, please tell me a solution.

Best regards,

Daisuke