• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 101 subscribers
  • Views 1771 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335x - Using GPMC and MMC1 interface

Siddharth Chowdhuri
Prodigy 120 points

Hi,

For one of our new proto, we require the following interfaces -
1. MMC1  - booting from eMMC flash (x8 wide)
2. GPMC -  SRAM interface to FPGA (x8 data width, separate address bus)

As the MMC1 and GPMC pins are multiplexed this will cause an issue and was planning to go with the following hardware implementation

Processor MMC/GPMC --> External Mux. (default option - MMC1) --> eMMC Flash over MMC1
Processor MMC/GPMC --> External Mux. (second option - GPMC ) --> FPGA  over SRAM i/f.

After  power up, the booting will be done over MMC1. After the booting is done (including Linux OS up and running)  -
1. Set the pins in the GPMC mode (for SRAM)

2. Select pin of external Mux (controlled from GPIO of Processor) to set the physical connection to FPGA.

3. Whenever the access to eMMC flash is required, the select pin of external mux will be set to default option and the pins to be set again in MMC1 mode.


Will this approach work with dynamic switching of pin mode during run time and what will be the limitations.

Regards,
Siddharth

  • 0
    TI__Guru*** 125430 points
    This sort of thing is not recommended. The pin muxing was not designed to handle it. There could be issues such as glitches being generated on the output or observed on the input when switching mux modes. I imagine it would "mostly" work, but I advise you to avoid dynamically changing the mux mode.
  • 0 in reply to Brad Griffis
    Prodigy 120 points

    Thanks Brad.

    We are planning to use e-MMC Flash for booting and storage. We need to have a high speed bi-directional communication bus between AM335x and FPGA for data transfer. We would prefer an SRAM type I/F.  Can you suggest the other alternate mechanism for the same.

    Regards,
    Siddharth

  • 0 in reply to Siddharth Chowdhuri
    TI__Guru*** 125430 points
    Have you tried the new "v3" pin mux tool? It has made great improvements in trying to find a workable set of pins.

    www.ti.com/.../pinmuxtool

    The GPMC is the only "SRAM type interface" on the device. You can try reducing the pin count by using address/data multiplexing or address/address/data (AAD) multiplexing. There are also multiple MMC ports. If you cannot find a workable option then perhaps another device like AM437x might work. (I haven't looked closely into its pin muxing, but I think it's certainly worth exploring if you can't get AM335x to work.)
  • 0 in reply to Brad Griffis
    Prodigy 120 points
    I've been using the V3 pin mux tool.

    1. One of the option that checked is to use LCD - LIDD Motorola 68K , 16-bit interface or LIDD Intel Async mode. Not sure of the effective through put and any example or reference for the same ?

    2. The other option is to use PRUSS mode - Direct connection for O/P - 8 bit mode (pru_r30[0:7]) without any pin conflict. If operated in this mode what would be the max rate of transfer ?

    Thanks & Regards,
    Siddharth
  • 0 in reply to Siddharth Chowdhuri
    TI__Guru*** 125430 points
    Please start separate threads for these questions. The people that know the answers will not be looking in this thread.

    Have you looked at AM437x? Its package has more pins and I think avoids some of these pin muxing limitations that you're experiencing. The GPMC is really the best suited for communication with an FPGA so I would recommend staying on that path.