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ARM core-tech A8 , APP

Akira Yoshimoto
Prodigy 710 points

Please tell the Q1-4 about AM3352BZCZD30 & Q5 for all devices that has ARM core-tech A8 ..
Q1 => The device can operate with 32 bit data only or can do with 64bit data for Multiplying or Accmulating ?
Q2 => A8 is only 32bit processor but A8 has VFP function that can operate 64bit data Multiplying or Accmulating with Double precision floating point  ?
Q3 => VFPv4 is one of A8’s fucntion ?
Q4=>  AM335x has VFP. Which sentence at the device data sheet tells the VFP function can operate 64bit data ..

http://www.ti.com/lit/ds/symlink/am3352.pdf

Q5=>  For TI devices having Cortex A8 ,  if VFP function enable or disable will be depending on devices  ,  Please tell me how to identify the status by the device data sheet  

 

  • 0
    TI__Guru**** 393215 points

    Hi,

    ARM specific documentation is available on the ARM support site: http://infocenter.arm.com/help/index.jsp

  • 0 in reply to Biser Gatchev-XID
    TI__Prodigy 710 points
    THanks !!but Enabling VFP or not seem to be the IC device specific
    so I need to get answer for Q1-4 at AM3352BZCZD30 and I would know how to identify which TI devices or TI SItara devices that has A8 core has VFP function ..
    regards
  • 0 in reply to Akira Yoshimoto
    TI__Guru**** 393215 points

    According to section 3.1.1 of the AM335X TRM Rev. L:

    • ARM Microprocessor

    – Cortex-A8

    – ARM Architecture version 7 ISA.

    – 2-issue, in-order execution pipeline.

    – L1 Instruction and Data Cache of 32KB, 4-way, 16-word line with 128-bit interface.

    – Integrated L2 cache of 256 KB, 8-way, 16 word line, 128 bit interface to L1 along with ECC/Parity supported.

    – Includes the Neon Media coprocessor (NEON™) which implements the Advanced SIMD media processing architecture.

    – Includes the VFP coprocessor which implements the VFPv3 architecture and is fully compliant with IEEE 754 standard.

    – The external interface uses the AXI protocol configured to 128-bit data width.

    – Includes the Embedded Trace Macrocell (ETM) support for non-invasive debugging.

    – Implements the ARMv7 debug with watch-point and breakpoint registers and 32-bit Advanced Peripheral Bus (APB) slave interface to CoreSight debug systems.

  • 0 in reply to Biser Gatchev-XID
    TI__Prodigy 710 points
    I read the manual about VFPthen Page131 tells
    =>You must set CPEXIST[11:10] to b11 to use the NEON or VFP coprocessor. All other
    CPEXIST bits must be set to 0."
    infocenter.arm.com/.../DDI0344K_cortex_a8_r3p2_trm.pdf
    Also I refere the following article
    =>VFP is a classic floating point hardware accelerator. It is not a parallel architecture like Neon. Basically it performs one operation on one set of inputs and returns one output. It's purpose is to speed up floating point calculations. It supports single and double precision floating point.
    stackoverflow.com/.../arm-cortex-a8-whats-the-difference-between-vfp-and-neon
    I understand can operate Multiplying or Accmulating on 64-bit double-precision values .
    But if VFP is uesed at the Device , CPEXIST must be set .
    then my questions are about AM335x Sitara
    1. Does the CPEXIST of AM335x Sitara sets to use VFP ?
    2. How to identify the device data sheet indication whether the CPEXIST of AM335x Sitara sets to use VFP or not
    3. the CPEXIST of AM335x setting is user accessible ? After TI ship out the product , customer can change the setting ?
  • 0 in reply to Akira Yoshimoto
    TI__Guru* 78305 points
    Hi Akira-san
    As discussed offline, based on the discussion your understanding below seens correct

    1. Does the CPEXIST of AM335x Sitara sets to use VFP ? => No , Disabled at Sitara by default
    2. How to identify whether the CPEXIST of AM335x Sitara sets to use VFP or not by that device data sheet ? => No sign at data sheet but Disabled at Sitara by default
    3. the CPEXIST of AM335x setting is user accessible ? After TI ship out the product , customer can change the setting ? => customer can set enable the assembly code at “How to enable NEON “

    Additional relevant links
    processors.wiki.ti.com/.../Cortex-A8

    you can use the Coprocessor Access Control Register (description here: infocenter.arm.com/.../index.jsp) to determine access permissions for the coprocessors. I think the wiki describes it well. This will allow software to determine if it is enabled/disabled, and potentially change its setting. Note that changes to this register may require certain privileged modes. Read the ARM TRM for more information.
  • 0 in reply to Mukul Bhatnagar
    TI__Prodigy 710 points
    I appriceiate to your answer .Mukul-san Thanks !!