This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

How does SD_HCTL[2] HSPE bit functio on Ti AM437x evm board for eMMC

Other Parts Discussed in Thread: TXS0108E

I tried to setting HSPE bit in SD_HCTL[2] when configure MMC controller to working at frequency as 48Mhz, however, it report Command CRC error in pending  interrupt after setting this bit.

I found OMAP4460 has such errata described in http://www.ti.com/lit/er/swpz017l/swpz017l.pdf

I want to know if AM437x has such errata? Thanks in advance!

  • Hi,

    I will forward his to the factory team for explanation.

  • You should be able to set that bit since the OMAP4 errata is only for OMAP4 and does not apply to AM437x. The controller in the AM437x is the same as the one on AM335x so I booted Linux on a Beaglebone Black off of a SanDisk Extreme card. I can see that the kernel driver set the bit:

    root@ubuntu-armhf:/sys/kernel/debug/mmc0# cat regs
    mmc0:
     ctx_loss:      1

    regs:
    CON:            0x00000600
    HCTL:           0x00000d06
    SYSCTL:         0x000e0087
    IE:             0x00000000
    ISE:            0x00000000
    CAPA:           0x06e10080
    root@ubuntu-armhf:/sys/kernel/debug/mmc0#

    I can get another card Wednesday and format for the AM437x GP EVM.

    Steve K.

  • I just noticed you were asking about eMMC. I'll have to check.

    Steve K.

  • Hi Steve.K,

    Thank you for your feedback, yes I'm using eMMC onboard chip which is connected to MMC1 on AM437x EVM board. 

  • I am confused about HSPE bit, MMCSD controller still works on 48Mhz even if this bit is NOT set, and SD card or eMMC chip works well on this frequency. However setting this bit would cause command timeout. Anyone knows if this bit is necessary for MMCSD operating at frequency higher than 25MHz?

  • The HSPE bit controls which clock edge changes the data output from AM437x.  When HSPE bit = 0, data changes on the falling edge of clock.  When HSPE bit = 1, data changes on the rising edge of clock. The proper setting of HSPE depends on the timing requirements/switching characteristics of the AM437x device and eMMC card combined with the PCB signal delays.

    The AM437x data sheet provides switching characteristics for both settings of the HSPE bit.  You should perform a timing analysis of your design to determine the proper way to set the HSPE bit.

    Regards,
    Paul

  • Hi Paul,

    Thank you very much for your update on this issue, could you please comment my understanding of your answer?

        Whether set/clear HSPE bit is determined by the hardware itself (TXS0108E switching and PCB layout would also impact the timing).

        On AM437X evm board, this bit should be cleared.

    Please let me know if I missed anything? Thanks.

  • The data output delay relative to the rising edge of clock must be evaluated to determine if data arrives at the eMMC pins such that data transitions do not violate setup and hold requirements of the eMMC device. The maximum data output delay of AM437x is combined with any external delays (propagation delay of the PCB and other devices in the path) to determine if the worst case maximum delay violates the min setup of the eMMC device. The minimum data output delay of AM437x is combined with any external delays to determine if the worst case minimum delay violates the min hold of the eMMC device. You must consider data delays relative to clock delays to determine the arrival of data relative to the clock.

    So yes, the setting of HSPE bit is determined by hardware. You need to perform timing analysis as described above to determine the best configuration of the HSPE bit. The HSPE bit allows you to shift the data by 1/2 clock cycle relative to clock, which may help met eMMC timing requirements. There is no guarantee either setting will satisfy your current system. Normally this timing analysis would have been done before the PCB design was completed in case signal trace lengths need to be adjusted to help resolve timing issues.

    I can't answer your question about the AM437x EVM since I didn't design the board. However, you should be able to reference the PCB design files to find trace lengths and perform the same analysis on the EVM.

    Regards,
    Paul

  • Hi Paul,

    Very appreciate for your detailed explanation, thank you very much.