Reading ADS1299 registers

Rahul,

What software are you using?

Hi Biser,

I am using spi protocol driver that is already available from ti kernel.When I say protocol driver I mean driver/spi/spi.c . I guess this has definition for spi_sync and spi_asunc, spi_message_add_tail() . I am using these functions for transfer of my spi data to my slave(ads chip). But the problem is after getting the first set clock and their data into the MOSI lines from Am437x . I am not getting any thing else on the bus that I am sending from my driver . So I wanted to know why is this so  ? My master(AM437x) clock for SPI transaction is 2 MHZ.

Thanks

rahul 

I will ask the SW team to explain SPI driver usage.

Hi Rahul,

This is done in spi-omap2-mcspi.c. Check static int omap2_mcspi_setup_transfer() function:

/* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS

* REVISIT: this controller could support SPI_3WIRE mode.

*/

if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {

         l &= ~OMAP2_MCSPI_CHCONF_IS;

         l &= ~OMAP2_MCSPI_CHCONF_DPE1;

         l |= OMAP2_MCSPI_CHCONF_DPE0;

} else {

         l |= OMAP2_MCSPI_CHCONF_IS;

         l |= OMAP2_MCSPI_CHCONF_DPE1;

        l &= ~OMAP2_MCSPI_CHCONF_DPE0;

}

/* wordlength */

l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;

l |= (word_len - 1) << 7;

/* set chipselect polarity; manage with FORCE */

if (!(spi->mode & SPI_CS_HIGH))

         l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */

else

        l &= ~OMAP2_MCSPI_CHCONF_EPOL;

/* set clock divisor */

l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;

l |= div << 2;

/* set SPI mode 0..3 */

if (spi->mode & SPI_CPOL)

         l |= OMAP2_MCSPI_CHCONF_POL;

else

        l &= ~OMAP2_MCSPI_CHCONF_POL;

if (spi->mode & SPI_CPHA)

        l |= OMAP2_MCSPI_CHCONF_PHA;

else

        l &= ~OMAP2_MCSPI_CHCONF_PHA;

mcspi_write_chconf0(spi, l);

cs->mode = spi->mode;

dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",

OMAP2_MCSPI_MAX_FREQ >> div,

(spi->mode & SPI_CPHA) ? "trailing" : "leading",

(spi->mode & SPI_CPOL) ? "inverted" : "normal");

return 0;

SPI FIFO is set in omap2_mcspi_set_fifo() function in the same driver. 

SPI controller has built in 64 byte buffer. It can be used either as a single 64 byte buffer, or, in some cases, as two separate 32 byte buffers. 

Best Regards, 
Yordan

Hi Yordan,

If I need to do a 24 bit message (MOSI)transfer I need to generate 24 bit clock(SCLK) . Then will setting member bits_per_word = 24 in my spi_transfer structure and then doing spi_message_add_tail and spi_sync do this job ?? or should I go with DMA in SPI . The thing is I do not want a delay in my clock cycle after every byte of transfer . Is there any thing like spi_transfer will do the transfer only in one byte format ?

Thanks
rahul

Hi yordan,

Now If I use DMA . the minimum bytes that are required for DAM is 160 . so now when I try doing a DMA transfer . Setting following : -

static int send_byte(struct my_dev *dev,int data){        

       struct spi_message msg = { };

       struct spi_transfer transfer = { };

       msg.actual_length = 170;

        msg.is_dma_mapped = 1;

        spi_message_init(&msg);

        dev->tx_buff[0] = data;

        transfer.tx_dma = dev->tx_buff; // tx_buff = devm_kzalloc(&spi->dev, SPI_BUFF_SIZE, GFP_KERNEL | GFP_DMA);

        transfer.rx_dma = dev->rx_buff;    // rx_buff = devm_kzalloc(&spi->dev, SPI_BUFF_SIZE, GFP_KERNEL | GFP_DMA);

        transfer.len = 170;

        transfer.speed_hz =SPI_BUS_SPEED_SLOW;

        spi_message_add_tail(&transfer, &msg);

        status = spi_sync(dev->spi, &msg);

      return status;

}

After this I ma getting an error in spi.c file saying :-

spi_master spi1: failed to transfer one message from queue . This message  popes form line : 603  of driver/spi/spi.c

How do I proceed ? Is this error due to my transfer size exceeding ? Do I have to use dma_alloc_coherent ? 

Thanks

rahul