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Sitara Clocks and PWM Options

Luis Cordova
Intellectual 1930 points

Hello,

I am wondering about the flexibility of the Sitara in generating clocks and PWM signals.

My first impression is that timer signals (timer4, timer5, etc.) output may work as PWM outputs once the dedicated PWM lines are full.

If this is the case, these PWM lines may hopefully be able to work as Clock signals as well.

Which peripherals would be best for generating clocks, and which would be best for PWM (after the eHRPWM and eCAP) signals?

Are the frequency of these signals configurable as well?

The highest frequency is 48MHz.

The closer the Sitara can operate like an FPGA for this application, the better.

Thanks

  • 0
    TI__Guru**** 393215 points

    Hi Luis,

    Which Sitara processor are you asking about?

  • 0 in reply to Biser Gatchev-XID
    TI__Intellectual 1930 points

    Hello Biser,

    I am asking about the AM335x. However, I would also like to know about the AM437x as well, since it has more PWM outputs available.

    Thanks

  • 0 in reply to Luis Cordova
    TI__Guru**** 393215 points

    AM335X has two dedicated clock outputs - CLKOUT1 and CLKOUT2. However they should not be used as a synchronous clock for any of the peripheral interfaces because they were not timing closed to any other signals. These clock outputs also were not designed to source any time critical external circuits that require a low jitter reference clock. The jitter performance of these outputs is unpredictable due to complex combinations of many system variables. For example, CLKOUT2 may be sourced from several PLLs with each PLL supporting many configurations that yield different jitter performance. There are also other  unpredictable contributors to jitter performance such as application specific noise or crosstalk into the clock circuits. Therefore, there are no plans to specify jitter performance for these outputs.

    AM437X has the same two clock sources, with the difference that CLKOUT2 can be configured to connect to a dedicated DPLL for providing clock to Ethernet PHYs.

    As for timer and PWM clock sources, and whether they will be usable, it depends what your clock requirements regarding stability and jitter would be. Generally the same notes for AM335X above would apply.

  • 0 in reply to Biser Gatchev-XID
    TI__Intellectual 1930 points
    Biser,

    Thank you for this excellent answer.

    So does the Sitara introduce more jitter into CLKOUT signals, even when they are sourced from PLL (assume no jitter)?

    If I understand correctly, the jitter will still be present and be unpredictable, but be minimal. This jitter is introduced by the complex combinations of the system variables.
  • 0 in reply to Luis Cordova
    TI__Guru 55305 points

    The PLL also contributes jitter.  All PLLs adjust their frequency outputs while tracking the reference clock.  This frequency variation will also appear as clock jitter.

    Regards,
    Paul