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Another CPPI USB DMA issue

Eilon Eyal74533

Intellectual 390 points

Hello,

I am using this post to reopen a previously opened post, which I mistakenly thought solved the issue. we still see the issue of DMA hang after applying the 5 patchs from TI (http://processors.wiki.ti.com/index.php/Sitara_Linux_MUSB_Issues#AMSDK_06.00.00.00

I am working a AM3356 based product which is connected to a USB modem through USB. The usb modem exports a composite usb interface composed from 2 CDC-ECM and 1 CDC-ACM. the Sitara is the USB host and the modem is the USB device.

we are using .SDK-06.00.00.00 with psp04.06.00.11 . the kernel is linux-3.2.0-psp04.06.00.11

during data transfers (around 2KB/S) we suddenly see the USB on the Sitara side stops and there is no way to recover except reboot. configuring the USB to use PIO instead of DMA seems to solve the issue, but we would like to use DMA since we expect much higher throughput (we hope to get ~60 Mbit/S)

while normal operation the regdeump shows:

USB (M)HDRC Register Du
FAddr : 00
Power : f0
Frame : 06df
Index : 0f
Testmode : 00
TxMaxPp : 0000
TxCSRp : 0000
RxMaxPp : 0000
RxCSR : 0000
RxCount : 0000
ConfigData : 33
DevCtl : 5d
MISC : 44
TxFIFOsz : 07
RxFIFOsz : 07
TxFIFOadd : 0780
RxFIFOadd : 0780
VControl : 00000000
HWVers : 0800
EPInfo : ff
RAMInfo : 0d
LinkInfo : 5c
VPLen : 3c
HS_EOF1 : 80
FS_EOF1 : 77
LS_EOF1 : 72
SOFT_RST : 00
DMA_CNTLch0 : 0000
DMA_ADDRch0 : 00000000
DMA_COUNTch0: 00000000
DMA_CNTLch1 : 0000
DMA_ADDRch1 : 00000000
DMA_COUNTch1: 00000000
DMA_CNTLch2 : 0000
DMA_ADDRch2 : 00000000
DMA_COUNTch2: 00000000
DMA_CNTLch3 : 0000
DMA_ADDRch3 : 00000000
DMA_COUNTch3: 00000000
DMA_CNTLch4 : 0000
DMA_ADDRch4 : 00000000
DMA_COUNTch4: 00000000
DMA_CNTLch5 : 0000
DMA_ADDRch5 : 00000000
DMA_COUNTch5: 00000000
DMA_CNTLch6 : 0000
DMA_ADDRch6 : 00000000
DMA_COUNTch6: 00000000
DMA_CNTLch7 : 0000
DMA_ADDRch7 : 00000000
DMA_COUNTch7: 00000000
#

and while the issues appears we see:

# cat regdump
MUSB (M)HDRC Register Dump
FAddr : 00
Power : e0
Frame : 051d
Index : 0f
Testmode : 00
TxMaxPp : 0000
TxCSRp : 0000
RxMaxPp : 0000
RxCSR : 0000
RxCount : 0000
ConfigData : 33
DevCtl : 19
MISC : 44
TxFIFOsz : 07
RxFIFOsz : 07
TxFIFOadd : 0780
RxFIFOadd : 0780
VControl : 00000000
HWVers : 0800
EPInfo : ff
RAMInfo : 0d
LinkInfo : 5c
VPLen : 3c
HS_EOF1 : 80
FS_EOF1 : 77
LS_EOF1 : 72
SOFT_RST : 00
DMA_CNTLch0 : 0000
DMA_ADDRch0 : 00000000
DMA_COUNTch0: 00000000
DMA_CNTLch1 : 0000
DMA_ADDRch1 : 00000000
DMA_COUNTch1: 00000000
DMA_CNTLch2 : 0000
DMA_ADDRch2 : 00000000
DMA_COUNTch2: 00000000
DMA_CNTLch3 : 0000
DMA_ADDRch3 : 00000000
DMA_COUNTch3: 00000000
DMA_CNTLch4 : 0000
DMA_ADDRch4 : 00000000
DMA_COUNTch4: 00000000
DMA_CNTLch5 : 0000
DMA_ADDRch5 : 00000000
DMA_COUNTch5: 00000000
DMA_CNTLch6 : 0000
DMA_ADDRch6 : 00000000
DMA_COUNTch6: 00000000
DMA_CNTLch7 : 0000
DMA_ADDRch7 : 00000000
DMA_COUNTch7: 00000000

could you please advise

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Forwarding this to the USB experts.

0 Bin Liu over 8 years ago

TI__Guru*** 125156 points

Eilon,

The regdump shows the modem has been disconnected. Does the serial console has any message when the problem happens?

Can you please kindly provide the link to the previous discussion?

Please try to collect the following information for investigation.

- 'cat /proc/driver/musb_hdrc.1' after the issue happened;

- Enable kernel DYNAMIC_DEBUG and enable dev_dbg logs in function ti81xx_interrupt(). Bascically, I'd like to see the logs of the following debug to check interrupt events right before the issue happens.

1081 dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Hi,
it took me sometime to reproduce the issue, attached are a new new dump files which represents the issue better:

## Before the issue happens ###
----- file : /sys/kernel/debug/musb-hdrc.0/regdump
MUSB (M)HDRC Register Dump
FAddr : 02
Power : f0
Frame : 009b
Index : 00
Testmode : 00
TxMaxPp : 0000
TxCSRp : 0000
RxMaxPp : 0000
RxCSR : 0000
RxCount : 0000
ConfigData : de
DevCtl : 99
MISC : 44
TxFIFOsz : 00
RxFIFOsz : 00
TxFIFOadd : 0000
RxFIFOadd : 0000
VControl : 00000000
HWVers : 0800
EPInfo : ff
RAMInfo : 0d
LinkInfo : 5c
VPLen : 3c
HS_EOF1 : 80
FS_EOF1 : 77
LS_EOF1 : 72
SOFT_RST : 00
DMA_CNTLch0 : 0000
DMA_ADDRch0 : 00000000
DMA_COUNTch0: 00000000
DMA_CNTLch1 : 0000
DMA_ADDRch1 : 00000000
DMA_COUNTch1: 00000000
DMA_CNTLch2 : 0000
DMA_ADDRch2 : 00000000
DMA_COUNTch2: 00000000
DMA_CNTLch3 : 0000
DMA_ADDRch3 : 00000000
DMA_COUNTch3: 00000000
DMA_CNTLch4 : 0000
DMA_ADDRch4 : 00000000
DMA_COUNTch4: 00000000
DMA_CNTLch5 : 0000
DMA_ADDRch5 : 00000000
DMA_COUNTch5: 00000000
DMA_CNTLch6 : 0000
DMA_ADDRch6 : 00000000
DMA_COUNTch6: 00000000
DMA_CNTLch7 : 0000
DMA_ADDRch7 : 00000000
DMA_COUNTch7: 00000000

----- file : /proc/driver/musb_hdrc.0
Status: MHDRC, Mode=Peripheral (Power=f0, DevCtl=99)
OTG state: b_peripheral; active
Options: ?dma?, otg (peripheral+host), [eps=16]
Peripheral address: 00
Root port status: 00000100
CPPI: txcr=0 txsrc=0 txena=0; rxcr=0 rxsrc=280de80 rxena=0
Gadget driver: g_cdc

ep0 (hw0): 1buf, csr 0000 maxp 0000
(queue empty)

ep1in (hw1): 1buf dma, csr 2403 maxp 0200
TX DMA0: 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
req cf492190, -820993808/-814996032
req cf4921d0, -820993808/-815746112
req cf492210, -820993808/-815778112
req cf492250, -820993808/-815744192
req cf492290, -820993808/-815743424
req cf4922d0, -820993808/-815778496
req cf492310, -820993808/-814995840
req cf492350, -820993808/-815745152
req cf492390, -820993808/-815744960
req cf4923d0, -820993808/-815880576

ep1out (hw1): 1buf dma, csr 2000 maxp 0200
RX DMA0: 2 left, 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
req cf50bdd0, -820993808/-821723648
req cf50be10, -820993808/-821723840
req cf50be50, -820993808/-821724224
req cf50be90, -820993808/-821724608
req cf50bed0, -820993808/-821724800
req cf50bf10, -820993808/-821726720
req cf50bf50, -820993808/-821724032
req cf50bf90, -820993808/-821725376
req cf50bfd0, -820993808/-821726528
req cf492150, -820993808/-821724416

ep2in (hw2): 1buf dma, csr 2403 maxp 0010
TX DMA1: 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
req cf492dd0, -820993808/-819242560

ep2out (hw2): 1buf dma, csr 2000 maxp 0200
RX DMA1: 268566788 left,00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
req cf50b8d0, -820993808/-814996800
req cf50b950, -820993808/-815776384
req cf50b990, -820993808/-815882112
req cf50b9d0, -820993808/-815776960
req cf50ba10, -820993808/-815777152
req cf50ba50, -820993808/-815768832
req cf50ba90, -820993808/-815291072
req cf50bad0, -820993808/-815290688
req cf50bb10, -820993808/-815290112
req cf50b910, -820993808/-815744384

ep3in (hw3): 1buf dma, csr 2404 maxp 0200
TX DMA2: 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
(queue empty)

ep3out (hw3): 1buf dma, csr 2000 maxp 0200
RX DMA2: 256 left, 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
req cf50b590, -820993808/-821723456
req cf50b5d0, -820993808/-821725568
req cf50b610, -820993808/-821725760
req cf50b3d0, -820993808/-821725952
req cf50b410, -820993808/-821726144
req cf50b450, -820993808/-821726912
req cf50b490, -820993808/-821727104
req cf50b4d0, -820993808/-821726336
req cf50b510, -820993808/-815745920
req cf50b550, -820993808/-821724992

ep4in (hw4): 1buf dma, csr 2404 maxp 0010
TX DMA3: 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
(queue empty)

ep4out (hw4): 1buf dma, csr 2000 maxp 0200
RX DMA3: 0 left, 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
req cf5ce690, -820993808/0
req cf5ce6d0, -820993808/0
req cf5ce710, -820993808/0
req cf5ce750, -820993808/0
req cf5ce790, -82cat: read error: Invalid argument

##### AFTER the issue happens
file--- /sys/kernel/debug/musb-hdrc.0/regdump
MUSB (M)HDRC Register Dump
FAddr : 02
Power : f0
Frame : 0046
Index : 00
Testmode : 00
TxMaxPp : 0000
TxCSRp : 0000
RxMaxPp : 0000
RxCSR : 0000
RxCount : 0000
ConfigData : de
DevCtl : 99
MISC : 44
TxFIFOsz : 00
RxFIFOsz : 00
TxFIFOadd : 0000
RxFIFOadd : 0000
VControl : 00000000
HWVers : 0800
EPInfo : ff
RAMInfo : 0d
LinkInfo : 5c
VPLen : 3c
HS_EOF1 : 80
FS_EOF1 : 77
LS_EOF1 : 72
SOFT_RST : 00
DMA_CNTLch0 : 0000
DMA_ADDRch0 : 00000000
DMA_COUNTch0: 00000000
DMA_CNTLch1 : 0000
DMA_ADDRch1 : 00000000
DMA_COUNTch1: 00000000
DMA_CNTLch2 : 0000
DMA_ADDRch2 : 00000000
DMA_COUNTch2: 00000000
DMA_CNTLch3 : 0000
DMA_ADDRch3 : 00000000
DMA_COUNTch3: 00000000
DMA_CNTLch4 : 0000
DMA_ADDRch4 : 00000000
DMA_COUNTch4: 00000000
DMA_CNTLch5 : 0000
DMA_ADDRch5 : 00000000
DMA_COUNTch5: 00000000
DMA_CNTLch6 : 0000
DMA_ADDRch6 : 00000000
DMA_COUNTch6: 00000000
DMA_CNTLch7 : 0000
DMA_ADDRch7 : 00000000
DMA_COUNTch7: 00000000

file --- /proc/driver/musb_hdrc.0
Status: MHDRC, Mode=Peripheral (Power=f0, DevCtl=99)
OTG state: b_peripheral; active
Options: ?dma?, otg (peripheral+host), [eps=16]
Peripheral address: 00
Root port status: 00000100
CPPI: txcr=0 txsrc=0 txena=0; rxcr=0 rxsrc=280de80 rxena=0
Gadget driver: g_cdc

ep0 (hw0): 1buf, csr 0000 maxp 0000
(queue empty)

ep1in (hw1): 1buf dma, csr 2404 maxp 0200
TX DMA0: 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
(queue empty)

ep1out (hw1): 1buf dma, csr 2000 maxp 0200
RX DMA0: 2 left, 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
req cf515f50, -821002000/-815131520
req cf515f90, -821002000/-815130176
req cf515fd0, -821002000/-821724032
req cf491150, -821002000/-815081856
req cf515dd0, -821002000/-815261248
req cf515e10, -821002000/-815000320
req cf515e50, -821002000/-815850112
req cf515e90, -821002000/-815318272
req cf515ed0, -821002000/-815851456
req cf515f10, -821002000/-815852032

ep2in (hw2): 1buf dma, csr 2404 maxp 0010
TX DMA1: 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
(queue empty)

ep2out (hw2): 1buf dma, csr 2000 maxp 0200
RX DMA1: 268566788 left,00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
req cf515a50, -821002000/-820444480
req cf515a90, -821002000/-815849728
req cf515ad0, -821002000/-820442944
req cf515b10, -821002000/-821726720
req cf5158d0, -821002000/-815079744
req cf515910, -821002000/-815132288
req cf515950, -821002000/-815320192
req cf515990, -821002000/-815317696
req cf5159d0, -821002000/-815850304
req cf515a10, -821002000/-815140480

ep3in (hw3): 1buf dma, csr 2404 maxp 0200
TX DMA2: 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
(queue empty)

ep3out (hw3): 1buf dma, csr 2000 maxp 0200
RX DMA2: 256 left, 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
req cf515450, -821002000/-815262400
req cf515490, -821002000/-820444672
req cf5154d0, -821002000/-815853376
req cf515510, -821002000/-820442176
req cf515550, -821002000/-815260864
req cf515590, -821002000/-814997824
req cf5155d0, -821002000/-820445056
req cf515610, -821002000/-820442752
req cf5153d0, -821002000/-815130944
req cf515410, -821002000/-815130560

ep4in (hw4): 1buf dma, csr 2404 maxp 0010
TX DMA3: 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
(queue empty)

ep4out (hw4): 1buf dma, csr 2000 maxp 0200
RX DMA3: 0 left, 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
req cf5d9550, -821002000/0
req cf5d9590, -821002000/0
req cf5d95d0, -821002000/0
req cf5d9610, -821002000/0
req cf5d9650, -821002000/0
req cf5d96d0, -821002000/0
req cf5d9710, -821002000/0
req cf5d9750, -821002000/0
req cf5d9790, -821002000/0
req cf5d97d0, -821002000/0
req cf5d9810, -821002000/0
req cf5d9850, -821002000/0
req cf5d9890, -821002000/0
req cf5d9910, -821002000/0
req cf5d9950, -821002000/0
req cf5d9990, -821002000/0

ep5in (hw5): 1buf dma, csr 2404 maxp 0200
TX DMA4: 0000000cat: read error: Invalid argument

Thanks a lot for the help

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

How often do you see the issue? How long does it take to happen?

Eilon Eyal74533 said:
## Before the issue happens ###
----- file : /sys/kernel/debug/musb-hdrc.0/regdump
......
DevCtl : 99
......
----- file : /proc/driver/musb_hdrc.0
Status: MHDRC, Mode=Peripheral (Power=f0, DevCtl=99)
OTG state: b_peripheral; active
......

ep3in (hw3): 1buf dma, csr 2404 maxp 0200
......
ep4in (hw4): 1buf dma, csr 2404 maxp 0010

Can you please double check the above log before the issue is the correct one? It shows the controller is already in an invalid state: the controller is in peripheral mode which has VBUS voltage >4.4V, and EP3IN and EP4IN have protocol errors which is that the host controller sent IN token 3 times but did not receive response from the device.

Can you use a protocol analyzer to capture a bus trace? I'd like to see what was happening on the bus. If the trace is too big to attach. I can provide a link to upload.

Is the USB0 port in host-only mode or OTG/DRD mode? Can you please share the Schematics?

Did you capture the interrupt log I asked? That can give a clue there is any event causes the controller disconnect the device.

0 Shabtai Haim over 8 years ago in reply to Bin Liu

Prodigy 60 points

Hi,

I cannot use protocol analyzer since the units are connected by hidden USB lines in the PCB.

The USB0 is host only mode.

I made a change at ti81xx.c - #define DEBUG before #include <linux/platform_device.h>

if (musb->int_usb & MUSB_INTR_SOF) {
musb->sof_cnt++;

Add the line - dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);

The following is a log of musb_hdrc.1.

cat /proc/driver/musb_hdrc.1
Status: MHDRC, Mode=Host (Power=e0, DevCtl=19)
OTG state: a_wait_bcon; inactive
Options: ?dma?, otg (peripheral+host), [eps=16]
Peripheral address: 00
Root port status: 00000100
CPPI: txcr=0 txsrc=0 txena=0; rxcr=0 rxsrc=280de80 rxena=0

Regards,
Shabtai

0 Bin Liu over 8 years ago in reply to Shabtai Haim

TI__Guru*** 125156 points

Shabtai Haim said:
I made a change at ti81xx.c - #define DEBUG before #include <linux/platform_device.h>

if (musb->int_usb & MUSB_INTR_SOF) {
musb->sof_cnt++;

Add the line - dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);

I am not sure what you were trying to do. But anyway please use the following instruction to generate the MUSB interrupt log.

1. build the kernel with DYNAMIC_DEBUG enabled;

2. after boot the board, run the following command.

# mount -t debugfs none /sys/kernel/debug
# echo 'func ti81xx_interrupt =p' > /sys/kernel/debug/dynamic_debug/control

3. replicate the issue, then run 'dmesg > musb.log' command to dump the kernel log to a file, and provide the log.

0 Shabtai Haim over 8 years ago in reply to Bin Liu

Prodigy 60 points

Hi,

How do I send/upload the log file ? I would prefer it won't published in forum

Regards,

Shabtai

0 Bin Liu over 8 years ago in reply to Shabtai Haim

TI__Guru*** 125156 points

This log should not have any secret. But you can contact your local TI FAE if you don't want to post it here.

0 Shabtai Haim over 8 years ago in reply to Bin Liu

Prodigy 60 points

[   33.599755] br0: port 1(usb0) entering forwarding state
[   33.679869] br1: port 1(usb1) entering forwarding state
[   33.685594] br1: port 2(eth1) entering forwarding state
[   34.519776] br0: port 2(eth0) entering forwarding state
[   54.343067]

#
#
# dmesg
, Rx 8
[   31.990207] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.990782] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   31.990873] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   31.991047] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.991146] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.991548] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   31.991633] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   31.991808] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.991936] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.992607] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   31.992931] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   31.993154] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.993264] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.993666] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   31.993728] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   31.993940] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.994013] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.994416] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   31.994477] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   31.994770] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.994844] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.995198] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.995289] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   31.995350] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   31.995381] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.995627] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.995734] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.996370] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   31.996431] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   31.996626] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.996698] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.997101] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   31.997161] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   31.997339] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.997412] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.998108] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   31.998170] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   31.998424] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.998553] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.999315] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.999397] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.999504] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   31.999576] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   31.999684] CPCAP get voltage
[   31.999793] CPCAP set voltage
[   31.999973] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.000064] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.000300] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.000424] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.000458] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.000565] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.000637] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.000754] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.001095] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.001231] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.001360] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.001481] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.001556] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.001618] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.001665] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.001766] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.001951] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.002116] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.002140] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.002224] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.002303] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.002348] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.002447] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.002478] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.002510] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.002617] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.002692] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.002767] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.002812] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.002922] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.003207] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.003363] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.004304] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.004451] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.004504] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.004603] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.005010] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.005129] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.005156] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.005268] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.005289] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.005387] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.005411] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.005515] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.005537] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.005639] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.006008] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.006131] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.006158] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.006269] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.006298] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.006398] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.009248] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.009366] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.009743] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.009911] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.010529] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.010636] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.010860] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.010991] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.011425] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.011534] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.011826] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.011945] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.012420] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.012516] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.017018] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.017161] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.017443] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.017542] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.017643] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.017678] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.017885] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.018052] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.018772] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.018855] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.019114] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.019216] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.020339] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.020453] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.020727] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.020852] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.021294] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.021396] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.021707] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.021860] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.022300] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.022405] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.022675] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.022797] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.023278] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.023382] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.023634] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.023802] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.024277] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.024377] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.026053] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.026195] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.026650] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.026743] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.027078] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.027177] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.027645] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.027726] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.028007] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.028103] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.028524] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.028602] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.029095] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.029194] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.029712] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.029807] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.030029] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.030234] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.030679] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.030794] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.031023] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.031154] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.031680] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.031805] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.032023] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.032167] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.032653] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.032762] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.033011] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.033135] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.033547] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.033650] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.034047] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.034216] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.034753] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.034849] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.035073] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.035198] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.035669] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.035773] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.036017] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.036139] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.036547] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.036647] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 8
[   32.036790] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.037091] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.037211] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.037648] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.037748] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.038015] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.038141] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.038296] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.038433] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.038456] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.038540] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.038633] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 8
[   32.038711] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.038831] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.039041] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.039170] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.039727] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.039845] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.040063] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.040198] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.040254] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.040358] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.040384] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.040496] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.040526] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.040617] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.041091] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.041214] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.041435] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.041557] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.042026] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.042067] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.042163] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.042188] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.042324] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.042350] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.042428] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.042520] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.042575] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.042676] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.043130] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.043236] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.043465] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.043587] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.044028] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.044070] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.044164] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.044321] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.044352] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.044387] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.044495] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.044527] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.044603] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.044700] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.045340] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.045442] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.045688] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.045806] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.046377] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.046432] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.046515] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.046633] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.046762] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.046920] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.047265] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.047368] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.047596] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.047731] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.048303] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.048408] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.048642] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.048790] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.049177] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.049276] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.049508] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.049662] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.050624] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.050734] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.050966] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.051146] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.051901] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.052003] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.052239] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.052394] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.053020] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.053117] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.053393] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.053465] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.053657] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.053792] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.054303] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.054404] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.054668] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.054835] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.055406] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.055510] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.055808] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.055974] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.056420] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.056520] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.056788] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.056909] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.057297] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.057396] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.067620] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.068072] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.068587] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.068725] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.071272] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.071722] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.072212] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.072351] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.072659] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.072729] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.072907] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.072989] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.073259] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.073353] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.073404] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.073494] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.073519] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.073611] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.073655] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.073722] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.073924] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.074022] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.074600] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.074676] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.074826] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.074921] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.075399] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.075474] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.076165] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.076260] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.076670] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.076747] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.077087] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.077175] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.077218] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.077312] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.077336] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.077437] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.077465] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.077558] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.077669] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.077759] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.078313] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.078403] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.078447] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.078537] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.078660] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.078751] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.078935] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.079026] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.079066] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.079158] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.079182] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.079282] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.079306] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.079403] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.079428] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.079529] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.079601] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.079736] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.079845] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.079934] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.079971] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.080064] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.080095] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.080195] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.080220] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.080325] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.080349] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.080439] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.080463] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.080567] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.080752] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.080839] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.080890] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.080976] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.081568] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.081746] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.081945] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.082064] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.082104] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.082199] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.082225] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.082330] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.082354] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.082461] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.082485] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.082585] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.082760] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.082872] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.082911] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.083011] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.083036] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.083140] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.083164] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.083254] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.083301] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.083382] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.083430] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.083504] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.083555] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.083641] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.083784] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.083919] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.083975] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.084026] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.084111] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.084141] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.084240] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.084265] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.084343] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.084377] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.084488] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.084513] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.084587] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.084677] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.084784] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.084918] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.085001] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.085026] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.085141] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.085167] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.085237] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.085260] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.085367] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.085392] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.085464] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.085507] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.085610] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.085689] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.085807] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.085943] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.086025] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.086053] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.086160] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.086185] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.086256] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.086347] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.086375] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.086471] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.086655] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.086771] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.087153] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.087261] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.087633] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.087765] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.088149] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.088253] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.088488] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.088604] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.089025] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.089124] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.089405] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.089576] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.090049] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.090151] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.090511] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.090630] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.090975] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.091078] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.091408] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.091526] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.091851] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.091947] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.092329] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.092479] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.092850] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.092946] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.093265] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.093380] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.093729] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.093823] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.094172] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.094284] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.094715] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.094814] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.095070] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.095185] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.095590] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.095695] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.096057] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.096173] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.096591] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.096687] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.096844] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.096954] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.097427] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.097526] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.097785] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.097930] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0
[   32.098094] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.103702] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.104456] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.105113] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.105279] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.105404] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.105526] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.106021] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.106159] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.106279] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.109969] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.115562] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.116643] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.117703] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.119301] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.119473] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.120389] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.120565] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.121524] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.121661] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.122040] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.122698] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.123528] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.125714] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.125896] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.126022] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.126144] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.126264] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.127165] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.129983] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.131451] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.142123] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.150567] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.151590] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.152659] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.153658] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.154051] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.155710] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.156682] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.157284] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.157425] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.157630] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.158070] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.158212] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.158335] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.158460] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.158923] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.159098] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.159220] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.159335] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.159454] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.159667] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.159752] CPCAP get voltage
[   32.160078] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.160206] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.160324] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.160449] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.160648] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.161060] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.161187] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.161310] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.161450] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.161559] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.162024] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.162160] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.162282] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.162400] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.163399] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.163727] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.164434] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.165123] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.165264] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.165387] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.165511] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.166000] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.166140] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.166264] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.172525] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.173540] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.174838] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.175672] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.184320] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.184482] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.184657] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.185081] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.185212] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.185352] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.185478] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.185739] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.186091] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.186221] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.190525] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.191583] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.192671] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.193959] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.195474] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.196684] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.197157] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.197296] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.197422] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.197537] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.198046] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.198179] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.198320] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.198438] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.198648] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.199160] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.200238] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.200413] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.200530] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.201395] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.201528] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.202033] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.202161] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.202278] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.202397] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.202526] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.202990] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.203140] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.203264] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.203387] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.203483] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.207112] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.207267] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.207399] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.207511] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.208020] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.208143] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.208262] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.208389] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.208512] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.208983] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.209139] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.209269] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.209363] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.209478] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.209962] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.210102] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.210222] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.210333] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.210453] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.210644] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.211076] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.211214] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.211339] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.211464] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.211654] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.212081] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.212212] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.212322] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.213357] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.213541] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.214060] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.214195] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.214318] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.214438] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.214638] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.215056] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.215197] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.215309] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.215432] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.215639] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.216152] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.216286] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.226771] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.227154] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.227298] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.227423] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.227543] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.227657] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.227768] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.227886] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.228012] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.228135] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.228237] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.228347] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.228463] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.228584] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.228695] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.228816] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.228929] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.229044] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.229161] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.229280] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.229400] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.229516] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.230020] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.230151] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.230275] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.231335] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.231515] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.232026] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.232162] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.232281] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.232416] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.232532] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.233030] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.233162] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.233295] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.233411] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.233532] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.234154] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.234268] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.234390] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.234513] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.234973] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.235114] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.235234] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.235348] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.235467] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.235661] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.236081] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.236214] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.236675] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.242523] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.243544] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.244592] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.245663] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.247127] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.247576] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.248454] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.249327] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.249517] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.259554] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.260170] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.260304] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.260424] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.260548] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.260667] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.260784] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.260905] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.261025] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.261662] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.261820] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.261941] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.262069] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.262189] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.262315] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.262463] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.262591] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.262719] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.262830] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.262943] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.263062] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.263181] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.263299] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.263415] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.263533] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.263654] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.263767] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.263883] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.264013] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.264134] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.264232] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.264359] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.264479] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.264597] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.264721] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.264840] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.264961] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.265081] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.265205] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.265325] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.265445] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.265567] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.265687] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.265807] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.265929] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.266045] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.266171] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.266360] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.273774] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.273908] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.274027] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.274149] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.274276] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.274898] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.275059] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.275186] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.275321] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.275450] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.275568] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.275692] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.275805] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.275922] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.276054] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.276170] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.276286] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.276718] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.276846] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.276962] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.277077] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.277190] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.277312] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.277429] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.277548] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.277673] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.277793] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.277915] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.278030] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.278154] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.278272] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.278400] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.278513] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.278637] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.278764] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.278886] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.279011] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.279137] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.279259] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.279370] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.279485] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.279618] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.279735] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.279850] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.280461] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.280618] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.280764] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.280887] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.281012] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.281121] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.281237] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.281361] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.281482] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.281605] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.281730] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.281849] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.281971] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.282095] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.282218] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.282344] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.282466] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.282588] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.282711] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.282834] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.282954] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.283081] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.283331] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.296555] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.296767] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.326608] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.469827] CPCAP get voltage
[   32.470332] CPCAP set voltage
[   32.489618] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   32.490505] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   32.490679] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   32.786548] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   33.489750] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   33.490768] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   33.490998] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   33.599755] br0: port 1(usb0) entering forwarding state
[   33.679869] br1: port 1(usb1) entering forwarding state
[   33.685594] br1: port 2(eth1) entering forwarding state
[   33.706576] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   33.952463] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   33.953161] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   33.953502] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   34.199959] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   34.200562] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   34.200797] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   34.490900] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   34.491611] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   34.491830] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   34.519776] br0: port 2(eth0) entering forwarding state
[   34.699824] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   34.700426] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   34.700666] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   35.490073] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   35.490614] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   35.490836] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   35.699802] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   35.700514] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   35.700777] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   36.490006] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   36.490681] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   36.490922] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   37.490056] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   37.490768] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   37.491010] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   37.699786] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   37.700483] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   37.700701] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   38.490049] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   38.490756] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   38.490999] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   39.490188] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   39.490859] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   39.491085] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   40.490123] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   40.490839] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   40.491057] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   41.490099] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   41.490662] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   41.490875] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   41.710071] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   41.710670] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   41.710920] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   42.490324] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   42.490904] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   42.491175] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   43.490132] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   43.490834] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   43.491059] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   44.223822] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   44.224631] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   44.224852] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   44.336841] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   44.337171] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   44.337308] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   44.337440] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   44.337568] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   44.490132] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   44.490704] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   44.490930] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   44.535379] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   44.536194] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   44.536427] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   45.490217] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   45.491233] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   45.491455] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   45.530091] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   45.531080] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   45.531260] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   45.726883] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   46.490230] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   46.491250] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   46.491495] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   47.490515] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   47.491446] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   47.491670] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   47.530170] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   47.531160] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   47.531341] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   47.726909] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   48.490079] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   48.491061] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   48.491286] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   49.490102] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   49.491085] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   49.491308] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   49.720389] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   49.721424] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   49.721738] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   49.920428] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   50.490494] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   50.491478] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   50.491696] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   50.880217] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   51.490078] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   51.491066] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   51.491467] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   51.540821] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   51.541783] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   51.541933] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   52.126979] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   52.490472] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   52.491499] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   52.491749] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   53.490523] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   53.491348] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   53.491581] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   54.343067]
[   54.490333] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   54.491164] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   54.491420] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   55.490365] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   55.491193] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   55.491415] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   56.490465] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   56.491172] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   56.491421] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   56.785568] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   56.786527] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   56.786849] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   57.490572] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   57.491142] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   57.491364] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   57.780159] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   57.780889] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   57.781117] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   57.926941] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   58.490334] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   58.491093] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   58.491311] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   59.490571] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   59.491329] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   59.491558] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   59.560277] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   59.560996] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   59.561219] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   59.780228] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   59.780916] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   59.781174] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   60.126952] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   60.127129] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   60.490363] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   60.491007] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   60.491267] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   60.523091] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   61.490612] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   61.491330] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   61.491553] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   62.028099] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   62.490599] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   62.491370] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   62.491587] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   63.490290] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   63.491048] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   63.491296] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   63.790398] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   63.791134] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   63.791353] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   64.326952] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
[   64.490543] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 0, Rx 2
[   64.491262] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 2, Rx 0
[   64.491499] musb-hdrc musb-hdrc.1: CPPI 4.1 IRQ: Tx 0, Rx 8
#

0 Rogerio Almeida over 8 years ago in reply to Shabtai Haim

TI__Mastermind 26025 points

Bin is traveling and he will reply once he is back.

0 Bin Liu over 8 years ago in reply to Shabtai Haim

TI__Guru*** 125156 points

Shabtai Haim said:

(Please visit the site to view this file)

I asked to capture the log with

# echo 'func ti81xx_interrupt =p' > /sys/kernel/debug/dynamic_debug/control

Not

# echo 'func cppi41dma_Interrupt =p' > /sys/kernel/debug/dynamic_debug/control

The log you provided is not what I am looking for.

0 Shabtai Haim over 8 years ago in reply to Bin Liu

Prodigy 60 points

Hi,

I run the following commands:

# mount -t debugfs none /sys/kernel/debug
# echo 'func ti81xx_interrupt =p' > /sys/kernel/debug/dynamic_debug/control

Regards,

Shabtai

0 Bin Liu over 8 years ago in reply to Shabtai Haim

TI__Guru*** 125156 points

Then please double check if you have run the command correctly.

The log you posted only has message "musb-hdrc musb-hdrc.x: CPPI 4.1 IRQ: Tx x, Rx x", this print statement is only in function cppi41dma_Interrupt().

If you had enabled debug for function ti81xx_interrupt(), the log should have message: "musb-hdrc musb-hdrc.x: usbintr (x) epintr(x)" instead.

0 Shabtai Haim over 8 years ago in reply to Bin Liu

Prodigy 60 points

Hi,

At file drivers/usb/musb/ti81cc.c, function static irqreturn_t ti81xx_interrupt(int irq, void *hci)

I added the line dev_dbg....

if (musb->int_usb & MUSB_INTR_SOF) {
musb->sof_cnt++;
dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr); // bsh007 - adding log to usb
musb->int_usb &= ~MUSB_INTR_SOF;

In kernal config - CONFIG_DYNAMIC_DEBUG=y .

I run it several times and got log (uploaded) and got log with the following line type:

[ 31.990207] musb-hdrc musb-hdrc.0: CPPI 4.1 IRQ: Tx 4, Rx 0

Can yo please send me the change needed for function ti81xx_interrupt().

Regards,
Shabtai

0 Bin Liu over 8 years ago in reply to Shabtai Haim

TI__Guru*** 125156 points

You don't need to modify anywhere in the kernel, just enable the debug and capture the log until the issue happens.

The dev_dbg() is right above 'if (musb->int_usb & MUSB_INTR_SOF)', you don't need to add it again.

Please post your ti81xx.c for me to check.

0 Shabtai Haim over 8 years ago in reply to Bin Liu

Prodigy 60 points

Hi,

Attached the file ti81xx.c

Regards,

Shabtai

ti81xx.c

/*
 * Texas Instruments TI81XX "usb platform glue layer"
 *
 * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
 *
 * Based on the DaVinci "glue layer" code.
 * Copyright (C) 2005-2006 by Texas Instruments
 *
 * This file is part of the Inventra Controller Driver for Linux.
 *
 * The Inventra Controller Driver for Linux is free software; you
 * can redistribute it and/or modify it under the terms of the GNU
 * General Public License version 2 as published by the Free Software
 * Foundation.
 *
 * The Inventra Controller Driver for Linux is distributed in
 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 * License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with The Inventra Controller Driver for Linux ; if not,
 * write to the Free Software Foundation, Inc., 59 Temple Place,
 * Suite 330, Boston, MA  02111-1307  USA
 *
 */


#include <linux/init.h>
#include <linux/io.h>
#include <linux/usb/otg.h>

#define DEBUG

#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>

#include "cppi41.h"
#include "ti81xx.h"

#include "musb_core.h"
#include "cppi41_dma.h"




#ifdef CONFIG_PM
struct ti81xx_usbss_regs {
	u32	sysconfig;

	u32	irq_en_set;

#ifdef CONFIG_USB_TI_CPPI41_DMA
	u32	irq_dma_th_tx0[4];
	u32	irq_dma_th_rx0[4];
	u32	irq_dma_th_tx1[4];
	u32	irq_dma_th_rx1[4];
	u32	irq_dma_en[2];

	u32	irq_frame_th_tx0[4];
	u32	irq_frame_th_rx0[4];
	u32	irq_frame_th_tx1[4];
	u32	irq_frame_th_rx1[4];
	u32	irq_frame_en[2];
#endif
};

struct ti81xx_usb_regs {
	u32	control;

	u32	irq_en_set[2];

#ifdef CONFIG_USB_TI_CPPI41_DMA
	u32	tx_mode;
	u32	rx_mode;
	u32	grndis_size[15];
	u32	auto_req;
	u32	teardn;
	u32	th_xdma_idle;
#endif
	u32	srp_fix;
	u32	phy_utmi;
	u32	mgc_utmi_loopback;
	u32	mode;
};
#endif

#define BABBLE_WORKAROUND_1 0
#define BABBLE_WORKAROUND_2 1
#define BABBLE_WORKAROUND_3 2

#define BABBLE_WORKAROUND (BABBLE_WORKAROUND_2)

struct ti81xx_glue {
	struct device *dev;
	struct resource *mem_pa;	/* usbss memory resource */
	void *mem_va;			/* ioremapped virtual address */
	struct platform_device *musb[2];/* child musb pdevs */
	u8	irq;			/* usbss irq */
	u8	first;			/* ignore first call of resume */
	int	context_loss_cnt;

#ifdef CONFIG_PM
	struct ti81xx_usbss_regs usbss_regs;
	struct ti81xx_usb_regs usb_regs[2];
#endif
};

static u64 musb_dmamask = DMA_BIT_MASK(32);
static void *usbss_virt_base;
static u8 usbss_init_done;
struct musb *gmusb[2];

u8 usbid_sw_ctrl;
#undef USB_TI81XX_DEBUG

#ifdef USB_TI81XX_DEBUG
#define	dprintk(x, ...) printk(x, ## __VA_ARGS__)
#else
#define dprintk(x, ...)
#endif

#ifdef CONFIG_USB_TI_CPPI41_DMA
static irqreturn_t cppi41dma_Interrupt(int irq, void *hci);
static u8 cppi41_init_done;
static void *cppi41_dma_base;
#define CPPI41_ADDR(offs) ((void *)((u32)cppi41_dma_base + (offs - 0x2000)))
#endif

extern void omap_ctrl_writel(u32 val, u16 offset);
extern u32 omap_ctrl_readl(u16 offset);

static inline u32 usbss_read(u32 offset)
{
	if (!usbss_init_done)
		return 0;
	return readl(usbss_virt_base + offset);
}

static inline void usbss_write(u32 offset, u32 data)
{
	if (!usbss_init_done)
		return ;
	writel(data, usbss_virt_base + offset);
}

static void usbotg_ss_init(void)
{
	if (!usbss_init_done) {
		usbss_init_done = 1;

		/* clear any USBSS interrupts */
		usbss_write(USBSS_IRQ_EOI, 0);
		usbss_write(USBSS_IRQ_STATUS, usbss_read(USBSS_IRQ_STATUS));
	}
}
static void usbotg_ss_uninit(void)
{
	if (usbss_init_done) {
		usbss_init_done = 0;
		usbss_virt_base = 0;
	}
}
void set_frame_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value, u8 en_intr)
{
	u32     base, reg_val, frame_intr = 0, frame_base = 0;
	u32     offs = epnum/4*4;
	u8      indx = (epnum % 4) * 8;

	if (is_tx)
		base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_TX1 :
				USBSS_IRQ_FRAME_THRESHOLD_TX0;
	else
		base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_RX1 :
				USBSS_IRQ_FRAME_THRESHOLD_RX0;

	reg_val = usbss_read(base + offs);
	reg_val &= ~(0xFF << indx);
	reg_val |= (value << indx);
	usbss_write(base + offs, reg_val);

	if (en_intr) {
		frame_base = musb->id ? USBSS_IRQ_FRAME_ENABLE_1 :
			USBSS_IRQ_FRAME_ENABLE_0;
		frame_intr = musb->id ? usbss_read(USBSS_IRQ_FRAME_ENABLE_0) :
			usbss_read(USBSS_IRQ_FRAME_ENABLE_1);
		frame_intr |= is_tx ? (1 << epnum) : (1 << (16 + epnum));
		usbss_write(frame_base, frame_intr);
		dev_dbg(musb->controller, "%s: framebase=%x, frame_intr=%x\n",
			is_tx ? "tx" : "rx", frame_base, frame_intr);
	}
}

void set_dma_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value)
{
	u32     base, reg_val;
	u32     offs = epnum/4*4;
	u8      indx = (epnum % 4) * 8;

	if (musb->id == 0)
		base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX0 :
				USBSS_IRQ_DMA_THRESHOLD_RX0;
	else
		base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX1 :
				USBSS_IRQ_DMA_THRESHOLD_RX1;

	reg_val = usbss_read(base + offs);
	reg_val &= ~(0xFF << indx);
	reg_val |= (value << indx);
	dev_dbg(musb->controller, "base=%x, offs=%x, indx=%d, reg_val = (%x)%x\n",
		base, offs, indx, reg_val, usbss_read(base + offs));
	usbss_write(base + offs, reg_val);
}

/* ti81xx specific read/write functions */
u16 ti81xx_musb_readw(const void __iomem *addr, unsigned offset)
{
	u32 tmp;
	u16 val;

	tmp = readl(addr + (offset & ~3));

	switch (offset & 0x3) {
	case 0:
		val = (tmp & 0xffff);
		break;
	case 1:
		val = (tmp >> 8) & 0xffff;
		break;
	case 2:
	case 3:
	default:
		val = (tmp >> 16) & 0xffff;
		break;
	}
	return val;
}

void ti81xx_musb_writew(void __iomem *addr, unsigned offset, u16 data)
{
	__raw_writew(data, addr + offset);
}

u8 ti81xx_musb_readb(const void __iomem *addr, unsigned offset)
{
	u32 tmp;
	u8 val;

	tmp = readl(addr + (offset & ~3));

	switch (offset & 0x3) {
	case 0:
		val = tmp & 0xff;
		break;
	case 1:
		val = (tmp >> 8);
		break;
	case 2:
		val = (tmp >> 16);
		break;
	case 3:
	default:
		val = (tmp >> 24);
		break;
	}
	return val;
}
void ti81xx_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
{
	__raw_writeb(data, addr + offset);
}

#ifdef CONFIG_USB_TI_CPPI41_DMA
/*
 * CPPI 4.1 resources used for USB OTG controller module:
 *
 tx/rx completion queues for usb0 */
static u16 tx_comp_q[] = {93, 94, 95, 96, 97,
				98, 99, 100, 101, 102,
				103, 104, 105, 106, 107 };

static u16 rx_comp_q[] = {109, 110, 111, 112, 113,
				114, 115, 116, 117, 118,
				119, 120, 121, 122, 123 };

/* tx/rx completion queues for usb1 */
static u16 tx_comp_q1[] = {125, 126, 127, 128, 129,
				 130, 131, 132, 133, 134,
				 135, 136, 137, 138, 139 };

static u16 rx_comp_q1[] = {141, 142, 143, 144, 145,
				 146, 147, 148, 149, 150,
				 151, 152, 153, 154, 155 };

/* Fair scheduling */
u32 dma_sched_table[] = {
	0x81018000, 0x83038202, 0x85058404, 0x87078606,
	0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x8f0f8e0e,
	0x91119010, 0x93139212, 0x95159414, 0x97179616,
	0x99199818, 0x9b1b9a1a, 0x9d1d9c1c, 0x00009e1e,
};

/* cppi41 dma tx channel info */
static const struct cppi41_tx_ch tx_ch_info[] = {
	[0] = {
		.port_num	= 1,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 32} , {0, 33} }
	},
	[1] = {
		.port_num	= 2,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 34} , {0, 35} }
	},
	[2] = {
		.port_num	= 3,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 36} , {0, 37} }
	},
	[3] = {
		.port_num	= 4,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 38} , {0, 39} }
	},
	[4] = {
		.port_num	= 5,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 40} , {0, 41} }
	},
	[5] = {
		.port_num	= 6,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 42} , {0, 43} }
	},
	[6] = {
		.port_num	= 7,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 44} , {0, 45} }
	},
	[7] = {
		.port_num	= 8,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 46} , {0, 47} }
	},
	[8] = {
		.port_num	= 9,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 48} , {0, 49} }
	},
	[9] = {
		.port_num	= 10,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 50} , {0, 51} }
	},
	[10] = {
		.port_num	= 11,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 52} , {0, 53} }
	},
	[11] = {
		.port_num	= 12,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 54} , {0, 55} }
	},
	[12] = {
		.port_num	= 13,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 56} , {0, 57} }
	},
	[13] = {
		.port_num	= 14,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 58} , {0, 59} }
	},
	[14] = {
		.port_num	= 15,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 60} , {0, 61} }
	},
	[15] = {
		.port_num	= 1,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 62} , {0, 63} }
	},
	[16] = {
		.port_num	= 2,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 64} , {0, 65} }
	},
	[17] = {
		.port_num	= 3,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 66} , {0, 67} }
	},
	[18] = {
		.port_num	= 4,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 68} , {0, 69} }
	},
	[19] = {
		.port_num	= 5,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 70} , {0, 71} }
	},
	[20] = {
		.port_num	= 6,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 72} , {0, 73} }
	},
	[21] = {
		.port_num	= 7,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 74} , {0, 75} }
	},
	[22] = {
		.port_num	= 8,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 76} , {0, 77} }
	},
	[23] = {
		.port_num	= 9,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 78} , {0, 79} }
	},
	[24] = {
		.port_num	= 10,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 80} , {0, 81} }
	},
	[25] = {
		.port_num	= 11,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 82} , {0, 83} }
	},
	[26] = {
		.port_num	= 12,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 84} , {0, 85} }
	},
	[27] = {
		.port_num	= 13,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 86} , {0, 87} }
	},
	[28] = {
		.port_num	= 14,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 88} , {0, 89} }
	},
	[29] = {
		.port_num	= 15,
		.num_tx_queue	= 2,
		.tx_queue	= { {0, 90} , {0, 91} }
	}
};

/* Queues 0 to 66 are pre-assigned, others are spare */
static const u32 assigned_queues[] = {	0x0,	    /* free queue 0..31 */
					0xffffffff, /* queue 32..63 */
					0xffffffff, /* queue 64..95 */
					0xffffffff, /* queue 96..127 */
					0x0fffffff  /* queue 128..155 */
					};

int __devinit cppi41_init(u8 id, u8 irq, int num_instances)
{
	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[id];
	u16 numch, blknum, order;
	u32 i;

	/* init cppi info structure  */
	cppi_info->dma_block = 0;
	for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
		cppi_info->ep_dma_ch[i] = i + (15 * id);

	cppi_info->q_mgr = 0;
	cppi_info->num_tx_comp_q = 15;
	cppi_info->num_rx_comp_q = 15;
	cppi_info->tx_comp_q = id ? tx_comp_q1 : tx_comp_q;
	cppi_info->rx_comp_q = id ? rx_comp_q1 : rx_comp_q;
	cppi_info->bd_intr_ctrl = 1;
	cppi_info->sched_tbl_ctrl = 0;
	cppi_info->version = usbss_read(USBSS_REVISION);

	if (cppi41_init_done)
		return 0;

	blknum = cppi_info->dma_block;

	/* Queue manager information */
	cppi41_queue_mgr[0].num_queue = 155;
	cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
						CPPI41_UNASSIGNED_QUEUE;
	cppi41_queue_mgr[0].base_fdbq_num = 0;
	cppi41_queue_mgr[0].assigned = assigned_queues;

	/* init DMA block */
	cppi41_dma_block[0].num_tx_ch = 30;
	cppi41_dma_block[0].num_rx_ch = 30;
	cppi41_dma_block[0].tx_ch_info = tx_ch_info;

	/* initilize cppi41 dma & Qmgr address */
	cppi41_dma_base = ioremap(TI81XX_USB_CPPIDMA_BASE,
					TI81XX_USB_CPPIDMA_LEN);

	cppi41_queue_mgr[0].q_mgr_rgn_base = CPPI41_ADDR(QMGR_RGN_OFFS);
	cppi41_queue_mgr[0].desc_mem_rgn_base = CPPI41_ADDR(QMRG_DESCRGN_OFFS);
	cppi41_queue_mgr[0].q_mgmt_rgn_base = CPPI41_ADDR(QMGR_REG_OFFS);
	cppi41_queue_mgr[0].q_stat_rgn_base = CPPI41_ADDR(QMGR_STAT_OFFS);
	cppi41_dma_block[0].global_ctrl_base = CPPI41_ADDR(DMA_GLBCTRL_OFFS);
	cppi41_dma_block[0].ch_ctrl_stat_base = CPPI41_ADDR(DMA_CHCTRL_OFFS);
	cppi41_dma_block[0].sched_ctrl_base = CPPI41_ADDR(DMA_SCHED_OFFS);
	cppi41_dma_block[0].sched_table_base = CPPI41_ADDR(DMA_SCHEDTBL_OFFS);

	/* Initialize for Linking RAM region 0 alone */
	cppi41_queue_mgr_init(cppi_info->q_mgr, 0, 0x3fff);

	numch =  USB_CPPI41_NUM_CH * 2 * num_instances;
	cppi41_dma_block[0].num_max_ch = numch;

	order = get_count_order(numch);

	/* TODO: check two teardown desc per channel (5 or 7 ?)*/
	if (order < 5)
		order = 5;

	cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
			dma_sched_table, numch);

	/* attach to the IRQ */
	if (request_irq(irq, cppi41dma_Interrupt, 0, "cppi41_dma", 0))
		printk(KERN_INFO "request_irq %d failed!\n", irq);
	else
		printk(KERN_INFO "registerd cppi-dma Intr @ IRQ %d\n", irq);

	cppi41_init_done = 1;

	printk(KERN_INFO "Cppi41 Init Done Qmgr-base(%p) dma-base(%p)\n",
		cppi41_queue_mgr[0].q_mgr_rgn_base,
		cppi41_dma_block[0].global_ctrl_base);

	/* enable all usbss the interrupts */
	usbss_write(USBSS_IRQ_EOI, 0);
	usbss_write(USBSS_IRQ_ENABLE_SET, USBSS_INTR_FLAGS);
	usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0xFFFeFFFe);

	printk(KERN_INFO "Cppi41 Init Done\n");

	return 0;
}

void cppi41_free(void)
{
	u32 numch, blknum, order;
	struct usb_cppi41_info *cppi_info = &usb_cppi41_info[0];

	if (!cppi41_init_done)
		return ;

	numch = cppi41_dma_block[0].num_max_ch;
	order = get_count_order(numch);
	blknum = cppi_info->dma_block;

	cppi41_dma_block_uninit(blknum, cppi_info->q_mgr, order,
			dma_sched_table, numch);
	cppi41_queue_mgr_uninit(cppi_info->q_mgr);

	iounmap(cppi41_dma_base);
	cppi41_dma_base = 0;
	cppi41_init_done = 0;
}

int cppi41_disable_sched_rx(void)
{
	cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
	return 0;
}

int cppi41_enable_sched_rx(void)
{
	cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
	return 0;
}

/*
 * Because we don't set CTRL.UINT, it's "important" to:
 *	- not read/write INTRUSB/INTRUSBE (except during
 *	  initial setup, as a workaround);
 *	- use INTSET/INTCLR instead.
 */

void txfifoempty_intr_enable(struct musb *musb, u8 ep_num)
{
	void __iomem *reg_base = musb->ctrl_base;
	u32 coremask;

	if (musb->txfifo_intr_enable) {
		coremask = musb_readl(reg_base, USB_CORE_INTR_SET_REG);
		coremask |= (1 << (ep_num + 16));
		musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
		dev_dbg(musb->controller, "enable txF intr ep%d coremask %x\n",
			ep_num, coremask);
	}
}

void txfifoempty_intr_disable(struct musb *musb, u8 ep_num)
{
	void __iomem *reg_base = musb->ctrl_base;
	u32 coremask;

	if (musb->txfifo_intr_enable) {
		coremask = (1 << (ep_num + 16));
		musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, coremask);
	}
}

#endif /* CONFIG_USB_TI_CPPI41_DMA */

int ti81xx_musb_enable_sof(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;

	if (musb->sof_enabled) {
		musb->sof_enabled++;
		return musb->sof_enabled;
	}

	musb->sof_enabled = 1;
	musb_writeb(musb->mregs, MUSB_INTRUSBE, MUSB_INTR_SOF |
		musb_readb(musb->mregs, MUSB_INTRUSBE));
	musb_writel(reg_base, USB_CORE_INTR_SET_REG, MUSB_INTR_SOF |
		musb_readl(reg_base, USB_CORE_INTR_SET_REG));

	return musb->sof_enabled;
}

int ti81xx_musb_disable_sof(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;
	u8 intrusb;

	if (musb->sof_enabled)
		musb->sof_enabled--;

	if (musb->sof_enabled)
		return musb->sof_enabled;

	intrusb = musb_readb(musb->mregs, MUSB_INTRUSBE);
	intrusb &= ~MUSB_INTR_SOF;
	musb_writeb(musb->mregs, MUSB_INTRUSBE, intrusb);
	musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, MUSB_INTR_SOF);
	musb->sof_enabled = 0;

	return 0;
}

/**
 * ti81xx_musb_enable - enable interrupts
 */
void ti81xx_musb_enable(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;
	u32 epmask, coremask;

	/* Workaround: setup IRQs through both register sets. */
	epmask = ((musb->epmask & USB_TX_EP_MASK) << USB_INTR_TX_SHIFT) |
	       ((musb->epmask & USB_RX_EP_MASK) << USB_INTR_RX_SHIFT);
	coremask = (0x01ff << USB_INTR_USB_SHIFT);

	coremask &= ~MUSB_INTR_SOF;

	musb_writel(reg_base, USB_EP_INTR_SET_REG, epmask);
	musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
	if (is_otg_enabled(musb))
		musb_writel(reg_base, USB_CORE_INTR_SET_REG,
			    USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT);
}

/**
 * ti81xx_musb_disable - disable HDRC and flush interrupts
 */
void ti81xx_musb_disable(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;

	musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, USB_INTR_USB_MASK);
	musb_writel(reg_base, USB_EP_INTR_CLEAR_REG,
			 USB_TX_INTR_MASK | USB_RX_INTR_MASK);
	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	musb_writel(reg_base, USB_IRQ_EOI, 0);
}

#define	POLL_SECONDS	2

static void otg_timer(unsigned long _musb)
{
	struct musb		*musb = (void *)_musb;
	void __iomem		*mregs = musb->mregs;
	u8			devctl;
	unsigned long		flags;

	/* We poll because DaVinci's won't expose several OTG-critical
	* status change events (from the transceiver) otherwise.
	 */
	devctl = musb_readb(mregs, MUSB_DEVCTL);
	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
			otg_state_string(musb->xceiv->state));

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_WAIT_BCON:
		devctl &= ~MUSB_DEVCTL_SESSION;
		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_HM) {
			musb->xceiv->state = OTG_STATE_A_IDLE;
			MUSB_HST_MODE(musb);
		} else {
			musb->xceiv->state = OTG_STATE_B_IDLE;
			MUSB_DEV_MODE(musb);
			mod_timer(&musb->otg_workaround,
					jiffies + POLL_SECONDS * HZ);
		}
		break;
	case OTG_STATE_A_WAIT_VFALL:
		if (!(devctl & MUSB_DEVCTL_SESSION)) {
			devctl |= MUSB_DEVCTL_SESSION;
			musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		}
		/*
		 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
		 * RTL seems to mis-handle session "start" otherwise (or in
		 * our case "recover"), in routine "VBUS was valid by the time
		 * VBUSERR got reported during enumeration" cases.
		 */
		if (devctl & MUSB_DEVCTL_VBUS) {
			mod_timer(&musb->otg_workaround,
					jiffies + POLL_SECONDS * HZ);
			break;
		}
		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
		musb_writel(musb->ctrl_base, USB_IRQ_STATUS_RAW_1,
			    MUSB_INTR_VBUSERROR << USB_INTR_USB_SHIFT);
		break;
	case OTG_STATE_B_IDLE:
		if (!is_peripheral_enabled(musb))
			break;

		/*
		 * There's no ID-changed IRQ, so we have no good way to tell
		 * when to switch to the A-Default state machine (by setting
		 * the DEVCTL.SESSION flag).
		 *
		 * Workaround:  whenever we're in B_IDLE, try setting the
		 * session flag every few seconds.  If it works, ID was
		 * grounded and we're now in the A-Default state machine.
		 *
		 * NOTE: setting the session flag is _supposed_ to trigger
		 * SRP but clearly it doesn't.
		 */
		devctl = musb_readb(mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_HM) {
			musb->xceiv->state = OTG_STATE_A_IDLE;
			break;
		}

		/* don't toggle SESSION flag if VBUS presents - connected
		 * to Host already
		 */
		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
			break;

		if ((devctl & MUSB_DEVCTL_SESSION) &&
				!(devctl & MUSB_DEVCTL_BDEVICE))
			devctl &= ~MUSB_DEVCTL_SESSION;
		else
			devctl |= MUSB_DEVCTL_SESSION;

		mod_timer(&musb->otg_workaround,
				jiffies + POLL_SECONDS * HZ);
		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
		break;
	default:
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}

void ti81xx_musb_try_idle(struct musb *musb, unsigned long timeout)
{
	if (!is_otg_enabled(musb))
		return;

	if (timeout == 0)
		timeout = jiffies + msecs_to_jiffies(3);

	/* Never idle if active, or when VBUS timeout is not set as host */
	if (musb->is_active || (musb->a_wait_bcon == 0 &&
				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
		dev_dbg(musb->controller, "%s active, deleting timer\n",
			otg_state_string(musb->xceiv->state));
		del_timer(&musb->otg_workaround);
		musb->last_timer = jiffies;
		return;
	}

	if (time_after(musb->last_timer, timeout) &&
					timer_pending(&musb->otg_workaround)) {
		dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
		return;
	}
	musb->last_timer = timeout;

	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
	    otg_state_string(musb->xceiv->state),
		jiffies_to_msecs(timeout - jiffies));
	mod_timer(&musb->otg_workaround, timeout);
}

#ifdef CONFIG_USB_TI_CPPI41_DMA
static irqreturn_t cppi41dma_Interrupt(int irq, void *hci)
{
	u32 intr_status;
	irqreturn_t ret = IRQ_NONE;
	u32 q_cmpl_status_0, q_cmpl_status_1, q_cmpl_status_2;
	u32 usb0_tx_intr, usb0_rx_intr;
	u32 usb1_tx_intr, usb1_rx_intr;
	void *q_mgr_base = cppi41_queue_mgr[0].q_mgr_rgn_base;
	unsigned long flags;

	/*
	 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
	 * don't get reflected in the interrupt source/mask registers.
	 */
	/*
	 * Check for the interrupts from Tx/Rx completion queues; they
	 * are level-triggered and will stay asserted until the queues
	 * are emptied.  We're using the queue pending register 0 as a
	 * substitute for the interrupt status register and reading it
	 * directly for speed.
	 */
	intr_status = usbss_read(USBSS_IRQ_STATUS);

	if (intr_status)
		usbss_write(USBSS_IRQ_STATUS, intr_status);
	else
		printk(KERN_DEBUG "spurious usbss intr\n");

	q_cmpl_status_0 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG2);
	q_cmpl_status_1 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG3);
	q_cmpl_status_2 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG4);

	/* USB0 tx/rx completion */
	/* usb0 tx completion interrupt for ep1..15 */
	usb0_tx_intr = (q_cmpl_status_0 >> 29) |
			((q_cmpl_status_1 & 0xFFF) << 3);
	usb0_rx_intr = ((q_cmpl_status_1 & 0x07FFe000) >> 13);

	usb1_tx_intr = (q_cmpl_status_1 >> 29) |
			((q_cmpl_status_2 & 0xFFF) << 3);
	usb1_rx_intr = ((q_cmpl_status_2 & 0x0fffe000) >> 13);

	/* get proper musb handle based usb0/usb1 ctrl-id */

	if (gmusb[0] && (usb0_tx_intr || usb0_rx_intr)) {
		dev_dbg(gmusb[0]->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n",
			usb0_tx_intr, usb0_rx_intr);
		spin_lock_irqsave(&gmusb[0]->lock, flags);
		cppi41_completion(gmusb[0], usb0_rx_intr,
					usb0_tx_intr);
		spin_unlock_irqrestore(&gmusb[0]->lock, flags);
		ret = IRQ_HANDLED;
	}

	if (gmusb[1] && (usb1_rx_intr || usb1_tx_intr)) {
		dev_dbg(gmusb[1]->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n",
			usb1_tx_intr, usb1_rx_intr);
		spin_lock_irqsave(&gmusb[1]->lock, flags);
		cppi41_completion(gmusb[1], usb1_rx_intr,
			usb1_tx_intr);
		spin_unlock_irqrestore(&gmusb[1]->lock, flags);
		ret = IRQ_HANDLED;
	}
	usbss_write(USBSS_IRQ_EOI, 0);

	return ret;
}
#endif

int musb_simulate_babble(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;
	void __iomem *mbase = musb->mregs;
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	u8 reg;

	/* during babble condition musb controller
	 * remove the session
	 */
	if (!data->babble_ctrl) {
		reg = musb_readb(mbase, MUSB_DEVCTL);
		reg &= ~MUSB_DEVCTL_SESSION;
		musb_writeb(mbase, MUSB_DEVCTL, reg);
		mdelay(100);
	}

	/* generate s/w babble interrupt */
	musb_writel(reg_base, USB_IRQ_STATUS_RAW_1, MUSB_INTR_BABBLE);
	return 0;
}
EXPORT_SYMBOL(musb_simulate_babble);

void musb_babble_workaround(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;

	ERR("Babble: devtcl(%x)Restarting musb....\n",
			 musb_readb(musb->mregs, MUSB_DEVCTL));

	/* Reset the controller */
	musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
	while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
		cpu_relax();

	/* Shutdown the on-chip PHY and its PLL. */
	if (data->set_phy_power)
		data->set_phy_power(musb->id, 0, false);
	udelay(100);

	musb_platform_set_mode(musb, MUSB_HOST);
	udelay(100);

	/* enable the usbphy */
	if (data->set_phy_power)
		data->set_phy_power(musb->id, 1, false);
	mdelay(100);

	/* re-setup the endpoint fifo addresses */
	if (musb->ops->reinit)
		musb->ops->reinit(plat->config->multipoint, musb);
	musb_start(musb);
}

void musb_babble_hwfix(struct musb *musb)
{
	int timeout = 10;
	u8 temp, session_restart = 0;

	/* wait for 320 clock cycles and check whether still babble
	 * present on the bus */
	udelay(6);

	temp = musb_readb(musb->mregs, MUSB_MISC);
	dev_dbg(musb->controller, "babble: MUSB MISC value %x\n", temp);

	/* check line monitor flag to check whether babble is
	 * due to noise
	 */
	dev_dbg(musb->controller, "STUCK_J is %s\n",
		temp & MUSB_MISC_STUCK_J ? "set" : "reset");

	if (temp & MUSB_MISC_STUCK_J) {
		/* babble is due to noise, then set transmit idle (d7 bit)
		 * to resume normal operation
		 */
		temp = musb_readb(musb->mregs, MUSB_MISC);
		temp |= MUSB_MISC_FORCE_TXIDLE;
		musb_writeb(musb->mregs, MUSB_MISC, temp);

		/* wait till line monitor flag cleared */
		dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n");
		do {
			temp = musb_readb(musb->mregs, MUSB_MISC);
			udelay(1);
		} while ((temp & MUSB_MISC_STUCK_J) && timeout--);

		/* check whether stuck_at_j bit cleared */
		temp = musb_readb(musb->mregs, MUSB_MISC);
		if (temp & MUSB_MISC_STUCK_J) {
			/* real babble condition is occured
			 * restart the controller to start the
			 * session again
			 */
			dev_dbg(musb->controller, "J not cleared, misc (%x)\n",
				temp);

			session_restart = 1;
		} else {
			u32 sofcnt;
			pr_info("babble: controller shall resume normal\n");
			/* check controller resumes normal operation
			 * by checking sof occurs for few frames
			 */
			sofcnt = musb->sof_cnt;
			ti81xx_musb_enable_sof(musb);
			udelay(280);
			if (musb->sof_cnt - sofcnt > 0)
				pr_info("babble: controller resumed normal\n");
			else {
				pr_info("babble: controller cannot resume\n");
				session_restart = 1;
			}
			ti81xx_musb_disable_sof(musb);
		}
	} else
		session_restart = 1;

	if (session_restart) {
		unsigned long flags;

		dev_dbg(musb->controller, "babble: restart controller\n");
		temp = musb_readb(musb->mregs, MUSB_DEVCTL);
		temp &= ~MUSB_DEVCTL_SESSION;
		musb_writeb(musb->mregs, MUSB_DEVCTL, temp);

		 /* inform stack about disconnect of root hub */
		spin_lock_irqsave(&musb->lock, flags);
		musb->int_usb = MUSB_INTR_DISCONNECT;
		musb_interrupt(musb);
		spin_unlock_irqrestore(&musb->lock, flags);

		/* restart the session */
		musb_babble_workaround(musb);
	}
}

static void evm_deferred_musb_restart(struct work_struct *work)
{
	struct musb *musb =
		container_of(work, struct musb, work);

	if (musb->enable_babble_work == BABBLE_WORKAROUND_3) {
		/* hw will not end the session  */
		musb_babble_hwfix(musb);
	} else {
		ERR("deferred musb restart musbid(%d)\n", musb->id);
		musb_babble_workaround(musb);
	}
}

static irqreturn_t ti81xx_interrupt(int irq, void *hci)
{
	struct musb  *musb = hci;
	void __iomem *reg_base = musb->ctrl_base;
	unsigned long flags;
	irqreturn_t ret = IRQ_NONE;
	u32 pend1 = 0, pend2 = 0;
	u32 epintr, usbintr;
	u8  is_babble = 0;
	int err;

	spin_lock_irqsave(&musb->lock, flags);

	/* Acknowledge and handle non-CPPI interrupts */
	/* Get endpoint interrupts */
	epintr = musb_readl(reg_base, USB_EP_INTR_STATUS_REG);
	musb->int_rx = (epintr & USB_RX_INTR_MASK) >> USB_INTR_RX_SHIFT;
	musb->int_tx = (epintr & USB_TX_INTR_MASK) >> USB_INTR_TX_SHIFT;
	if (epintr)
		musb_writel(reg_base, USB_EP_INTR_STATUS_REG, epintr);

	/* Get usb core interrupts */
	usbintr = musb_readl(reg_base, USB_CORE_INTR_STATUS_REG);
	if (!usbintr && !epintr) {
		dev_dbg(musb->controller, "sprious interrupt\n");
		goto eoi;
	}

	if (usbintr)
		musb_writel(reg_base, USB_CORE_INTR_STATUS_REG, usbintr);
	musb->int_usb =	(usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;

	//dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);

	if (musb->int_usb & MUSB_INTR_SOF) {
		musb->sof_cnt++;
		dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);  // bsh007 - adding log to usb
		musb->int_usb &= ~MUSB_INTR_SOF;
#ifdef CONFIG_USB_TI_CPPI41_DMA
		if (musb->tx_isoc_sched_enable)
			cppi41_isoc_schedular(musb);
#endif
		ret = IRQ_HANDLED;
	}

	if (musb->txfifo_intr_enable && (usbintr & USB_INTR_TXFIFO_MASK)) {
#ifdef CONFIG_USB_TI_CPPI41_DMA
		dev_dbg(musb->controller,
			"TxFIFOIntr %x\n", usbintr >> USB_INTR_TXFIFO_EMPTY);
		cppi41_handle_txfifo_intr(musb,
				usbintr >> USB_INTR_TXFIFO_EMPTY);
		ret = IRQ_HANDLED;
#endif
	}
	usbintr &= ~USB_INTR_TXFIFO_MASK;

	/*
	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
	 * AM3517's missing ID change IRQ.  We need an ID change IRQ to
	 * switch appropriately between halves of the OTG state machine.
	 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
	 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
	 */
	if ((usbintr & MUSB_INTR_BABBLE) && is_otg_enabled(musb)
		&& (musb->xceiv->state == OTG_STATE_A_HOST))
		is_babble = 1;
	else if ((usbintr & MUSB_INTR_BABBLE) && !is_otg_enabled(musb)
		&& is_host_enabled(musb))
			is_babble = 1;

	if (is_babble) {
		if (musb->enable_babble_work != BABBLE_WORKAROUND_3)
			musb->int_usb = MUSB_INTR_DISCONNECT;

		ERR("CAUTION: musb%d: Babble Interrupt Occured\n", musb->id);
	}

	err = is_host_enabled(musb) && (musb->int_usb &
			MUSB_INTR_VBUSERROR);

	if (err || (usbintr & (USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT))) {
		int drvvbus = musb_readl(reg_base, USB_STAT_REG);
		void __iomem *mregs = musb->mregs;
		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);

		if (err) {
			/*
			 * The Mentor core doesn't debounce VBUS as needed
			 * to cope with device connect current spikes. This
			 * means it's not uncommon for bus-powered devices
			 * to get VBUS errors during enumeration.
			 *
			 * This is a workaround, but newer RTL from Mentor
			 * seems to allow a better one: "re"-starting sessions
			 * without waiting for VBUS to stop registering in
			 * devctl.
			 */
			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
			mod_timer(&musb->otg_workaround,
						jiffies + POLL_SECONDS * HZ);
			WARNING("VBUS error workaround (delay coming)\n");
		} else if (is_host_enabled(musb) && drvvbus) {
			if ((devctl & MUSB_DEVCTL_SESSION) &&
				!(devctl & MUSB_DEVCTL_BDEVICE) &&
				!(devctl & MUSB_DEVCTL_HM)) {
				dev_dbg(musb->controller,
					"Only micro-A plug is connected\n");
			} else {
				if (musb->is_active)
					del_timer(&musb->otg_workaround);
				else
					musb->is_active = 1;

				MUSB_HST_MODE(musb);
				musb->xceiv->default_a = 1;
				musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
			}
		} else {
			musb->is_active = 0;
			MUSB_DEV_MODE(musb);
			musb->xceiv->default_a = 0;
			musb->xceiv->state = OTG_STATE_B_IDLE;
		}

		/* NOTE: this must complete power-on within 100 ms. */
		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
				drvvbus ? "on" : "off",
				otg_state_string(musb->xceiv->state),
				err ? " ERROR" : "",
				devctl);
		ret = IRQ_HANDLED;
	}

	if (musb->int_tx || musb->int_rx || musb->int_usb)
		ret |= musb_interrupt(musb);

 eoi:
	/* EOI needs to be written for the IRQ to be re-asserted. */
	if (ret == IRQ_HANDLED || epintr || usbintr) {
		/* write EOI */
		musb_writel(reg_base, USB_IRQ_EOI, 1);
	}

	/* Poll for ID change */
	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
		mod_timer(&musb->otg_workaround, jiffies + POLL_SECONDS * HZ);

	spin_unlock_irqrestore(&musb->lock, flags);

	if (ret != IRQ_HANDLED) {
		if (epintr || usbintr)
			/*
			 * We sometimes get unhandled IRQs in the peripheral
			 * mode from EP0 and SOF...
			 */
			dev_dbg(musb->controller, "Unhandled USB IRQ %08x-%08x\n",
					 epintr, usbintr);
		else if (printk_ratelimit())
			/*
			 * We've seen series of spurious interrupts in the
			 * peripheral mode after USB reset and then after some
			 * time a real interrupt storm starting...
			 */
			dev_dbg(musb->controller, "Spurious IRQ, CPPI 4.1 status %08x, %08x\n",
					 pend1, pend2);
	}

	if (is_babble) {
		if (musb->enable_babble_work)
			schedule_work(&musb->work);
		else {
			musb_writeb(musb->mregs, MUSB_DEVCTL,
				musb_readb(musb->mregs, MUSB_DEVCTL) |
				MUSB_DEVCTL_SESSION);
		}
	}
	return ret;
}
int ti81xx_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	void __iomem *reg_base = musb->ctrl_base;
	u32 regval;

	/* TODO: implement this using CONF0 */
	if (musb_mode == MUSB_HOST) {
		regval = musb_readl(reg_base, USB_MODE_REG);

		regval &= ~USBMODE_USBID_HIGH;
		if (usbid_sw_ctrl && cpu_is_ti816x())
			regval |= USBMODE_USBID_MUXSEL;

		musb_writel(reg_base, USB_MODE_REG, regval);
		musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
		dev_dbg(musb->controller, "host: value of mode reg=%x regval(%x)\n",
			musb_readl(reg_base, USB_MODE_REG), regval);
	} else if (musb_mode == MUSB_PERIPHERAL) {
		/* TODO commmented writing 8 to USB_MODE_REG device
			mode is not working */
		regval = musb_readl(reg_base, USB_MODE_REG);

		regval |= USBMODE_USBID_HIGH;
		if (usbid_sw_ctrl && cpu_is_ti816x())
			regval |= USBMODE_USBID_MUXSEL;

		musb_writel(reg_base, USB_MODE_REG, regval);
		dev_dbg(musb->controller, "device: value of mode reg=%x regval(%x)\n",
			musb_readl(reg_base, USB_MODE_REG), regval);
	} else if (musb_mode == MUSB_OTG) {
		musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
	} else
		return -EIO;

	return 0;
}

int ti81xx_musb_init(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	u32 rev;
	u8 mode;

	if (musb->id < 2)
		gmusb[musb->id] = musb;

	usb_nop_xceiv_register(musb->id);

	musb->xceiv = otg_get_transceiver(musb->id);
	if (!musb->xceiv)
		return -ENODEV;

	/* mentor is at offset of 0x400 in am3517/ti81xx */
	musb->mregs += USB_MENTOR_CORE_OFFSET;

	/* Returns zero if e.g. not clocked */
	rev = musb_readl(reg_base, USB_REVISION_REG);
	if (!rev)
		return -ENODEV;

	pr_info("MUSB%d controller's USBSS revision = %08x\n", musb->id, rev);

	if (is_host_enabled(musb))
		setup_timer(&musb->otg_workaround, otg_timer,
					(unsigned long) musb);

	/* Reset the controller */
	musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);

	/* wait till reset bit clears */
	while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
		cpu_relax();

	/* Start the on-chip PHY and its PLL with PHYWKUP disabled */
	if (data->set_phy_power)
		data->set_phy_power(musb->id, 1, false);

	musb->a_wait_bcon = A_WAIT_BCON_TIMEOUT;
	musb->isr = ti81xx_interrupt;

	if (cpu_is_ti816x())
		usbid_sw_ctrl = 1;

	if (is_otg_enabled(musb)) {
		/* if usb-id contolled through software for ti816x then
		 * configure the usb0 in peripheral mode and usb1 in
		 * host mode
		*/
		if (usbid_sw_ctrl && cpu_is_ti816x())
			mode = musb->id ? MUSB_HOST : MUSB_PERIPHERAL;
		else
			mode = MUSB_OTG;
	} else
		/* set musb controller to host mode */
		mode = is_host_enabled(musb) ? MUSB_HOST : MUSB_PERIPHERAL;

	/* set musb controller to host mode */
	musb_platform_set_mode(musb, mode);

#ifdef CONFIG_USB_TI_CPPI41_DMA
	/* TxFifo empty interrupt logic is supported
	 * only for isochronous tranfers only
	 */
	musb->txfifo_intr_enable = data->txfifo_intr_enable;
	musb->tx_isoc_sched_enable = data->tx_isoc_sched_enable;

	if (musb->tx_isoc_sched_enable) {
		if (musb->txfifo_intr_enable) {
			musb->txfifo_intr_enable = 0;
			dev_dbg(musb->controller, "disable txfifo intr"
				" logic disabled\n");
		}
		dev_dbg(musb->controller, "tx-isoc-schedular logic enabled\n");
	}

	if (musb->txfifo_intr_enable)
		printk(KERN_DEBUG "TxFifo Empty intr enabled\n");
	else
		printk(KERN_DEBUG "TxFifo Empty intr disabled\n");

	/* enable rxdma GRNDIS mode, as Extra IN token
	 * issue fixed in PG2.0 RTL
	 */
	if (data->grndis_for_host_rx)
		usb_cppi41_info[musb->id].rx_dma_mode = USB_GENERIC_RNDIS_MODE;
#endif
	/* enable babble workaround */
	INIT_WORK(&musb->work, evm_deferred_musb_restart);
	musb->enable_babble_work = 0;

	musb->enable_babble_work = BABBLE_WORKAROUND;
	musb_writel(reg_base, USB_IRQ_EOI, 0);

	if (data->babble_ctrl) {
		u8 temp;
		/* enable s/w controlled session bit during
		 * babble condition
		 */
		temp = musb_readb(musb->mregs, MUSB_MISC);
		temp |= MUSB_MISC_SW_SESSION_CTRL;
		musb_writeb(musb->mregs, MUSB_MISC, temp);

		musb->enable_babble_work = BABBLE_WORKAROUND_3;
		pr_info("musb%d: Enabled SW babble control\n", musb->id);
		dev_dbg(musb->controller, "musb.misc regval %x\n",
			musb_readb(musb->mregs, MUSB_MISC));
	}

	return 0;
}

/* TI81xx supports only 32bit read operation */
void ti81xx_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	void __iomem *fifo = hw_ep->fifo;
	u32		val;
	int		i;

	/* Read for 32bit-aligned destination address */
	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
		readsl(fifo, dst, len >> 2);
		dst += len & ~0x03;
		len &= 0x03;
	}
	/*
	 * Now read the remaining 1 to 3 byte or complete length if
	 * unaligned address.
	 */
	if (len > 4) {
		for (i = 0; i < (len >> 2); i++) {
			*(u32 *) dst = musb_readl(fifo, 0);
			dst += 4;
		}
		len &= 0x03;
	}
	if (len > 0) {
		val = musb_readl(fifo, 0);
		memcpy(dst, &val, len);
	}
}

int ti81xx_musb_exit(struct musb *musb)
{
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;

	if (is_host_enabled(musb))
		del_timer_sync(&musb->otg_workaround);

	/* Shutdown the on-chip PHY and its PLL. */
	if (data->set_phy_power)
		data->set_phy_power(musb->id, 0, false);

	otg_put_transceiver(musb->xceiv);
	usb_nop_xceiv_unregister(musb->id);

	return 0;
}

static struct musb_platform_ops ti81xx_ops = {
	.fifo_mode	= 4,
	.flags		= MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
	.init		= ti81xx_musb_init,
	.exit		= ti81xx_musb_exit,

	.enable		= ti81xx_musb_enable,
	.disable	= ti81xx_musb_disable,

	.try_idle	= ti81xx_musb_try_idle,
	.set_mode	= ti81xx_musb_set_mode,

	.read_fifo      = ti81xx_musb_read_fifo,
	.write_fifo     = musb_write_fifo,

	.dma_controller_create	= cppi41_dma_controller_create,
	.dma_controller_destroy	= cppi41_dma_controller_destroy,
	.simulate_babble_intr	= musb_simulate_babble,
#ifdef CONFIG_USB_TI_CPPI41_DMA
	.txfifoempty_intr_enable = txfifoempty_intr_enable,
	.txfifoempty_intr_disable = txfifoempty_intr_disable,
#endif
	.reinit = musb_reinit,
	.enable_sof = ti81xx_musb_enable_sof,
	.disable_sof = ti81xx_musb_disable_sof
};

static void __devexit ti81xx_delete_musb_pdev(struct ti81xx_glue *glue, u8 id)
{
	platform_device_del(glue->musb[id]);
	platform_device_put(glue->musb[id]);
}

static int __devinit ti81xx_create_musb_pdev(struct ti81xx_glue *glue, u8 id)
{
	struct device *dev = glue->dev;
	struct platform_device *pdev = to_platform_device(dev);
	struct musb_hdrc_platform_data  *pdata = dev->platform_data;
	struct omap_musb_board_data *bdata = pdata->board_data;
	struct platform_device	*musb;
	struct resource *res;
	struct resource	resources[2];
	char res_name[10];
	int ret = 0;

	/* get memory resource */
	sprintf(res_name, "musb%d", id);
	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
	if (!res) {
		dev_err(dev, "%s get mem resource failed\n", res_name);
		ret = -ENODEV;
		goto err0;
	}
	res->parent = NULL;
	resources[0] = *res;

	/* get irq resource */
	sprintf(res_name, "musb%d-irq", id);
	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
	if (!res) {
		dev_err(dev, "%s get irq resource failed\n", res_name);
		ret = -ENODEV;
		goto err0;
	}
	res->parent = NULL;
	resources[1] = *res;

	/* allocate the child platform device */
	musb = platform_device_alloc("musb-hdrc", id);
	if (!musb) {
		dev_err(dev, "failed to allocate musb device\n");
		goto err0;
	}

	musb->id			= id;
	musb->dev.parent		= dev;
	musb->dev.dma_mask		= &musb_dmamask;
	musb->dev.coherent_dma_mask	= musb_dmamask;

	glue->musb[id]			= musb;

	pdata->platform_ops		= &ti81xx_ops;

	ret = platform_device_add_resources(musb, resources, 2);
	if (ret) {
		dev_err(dev, "failed to add resources\n");
		goto err1;
	}

	if (id == 0)
		pdata->mode = bdata->mode & USB0PORT_MODEMASK;
	else
		pdata->mode = (bdata->mode & USB1PORT_MODEMASK)
					>> USB1PORT_MODESHIFT;

	dev_info(dev, "musb%d, board_mode=0x%x, plat_mode=0x%x\n",
					id, bdata->mode, pdata->mode);

	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	if (ret) {
		dev_err(dev, "failed to add platform_data\n");
		goto err1;
	}

	ret = platform_device_add(musb);
	if (ret) {
		dev_err(dev, "failed to register musb device\n");
		goto err1;
	}

	return 0;

err1:
	platform_device_put(musb);
err0:
	return ret;
}

static int __init ti81xx_probe(struct platform_device *pdev)
{
	struct ti81xx_glue *glue;
	struct device *dev = &pdev->dev;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	int ret = 0, i;
	struct resource *res;

	/* allocate glue */
	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	if (!glue) {
		dev_err(&pdev->dev, "unable to allocate glue memory\n");
		ret = -ENOMEM;
		goto err0;
	}

	/* get memory resource */
	glue->mem_pa = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!glue->mem_pa) {
		dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
		ret = -ENODEV;
		goto err1;
	}

	/* get memory resource */
	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "usbss-irq");
	if (!res) {
		dev_err(&pdev->dev, "failed to get usbss irq resourse\n");
		ret = -ENODEV;
		goto err1;
	}
	glue->irq = res->start;

	/* iomap for usbss mem space */
	glue->mem_va =
		ioremap(glue->mem_pa->start, resource_size(glue->mem_pa));
	if (!glue->mem_va) {
		dev_err(&pdev->dev, "usbss ioremap failed\n");
		ret = -ENOMEM;
		goto err1;
	}
	usbss_virt_base = glue->mem_va;

	glue->first = 1;
	glue->dev = &pdev->dev;
	platform_set_drvdata(pdev, glue);

	/* enable clocks */
	pm_runtime_enable(&pdev->dev);
	ret = pm_runtime_get_sync(&pdev->dev);
	if (ret < 0) {
		dev_err(dev, "pm_runtime_get_sync FAILED");
		goto err2;
	}

	/* usb subsystem init */
	usbotg_ss_init();

	/* clear any USBSS interrupts */
	writel(0, glue->mem_va + USBSS_IRQ_EOI);
	writel(readl(glue->mem_va + USBSS_IRQ_STATUS),
					glue->mem_va + USBSS_IRQ_STATUS);

	/* create the child platform device for mulitple instances of musb */
	for (i = 0; i <= data->instances; ++i) {
#ifdef CONFIG_USB_TI_CPPI41_DMA
		/* initialize the cppi41dma init */
		cppi41_init(i, glue->irq, data->instances+1);
#endif
		ret = ti81xx_create_musb_pdev(glue, i);
		if (ret != 0)
			goto err3;
	}

	return 0;

err3:
	pm_runtime_put_sync(&pdev->dev);
err2:
	pm_runtime_disable(&pdev->dev);
	iounmap(glue->mem_va);
err1:
	kfree(glue);
err0:
	return ret;
}

static int __exit ti81xx_remove(struct platform_device *pdev)
{
	struct ti81xx_glue *glue = platform_get_drvdata(pdev);
	struct device *dev = &pdev->dev;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	int i;

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	/* delete the child platform device for mulitple instances of musb */
	for (i = 0; i <= data->instances; ++i)
		ti81xx_delete_musb_pdev(glue, i);

#ifdef CONFIG_USB_TI_CPPI41_DMA
	cppi41_free();
#endif
	/* iounmap */
	iounmap(glue->mem_va);
	usbotg_ss_uninit();

	kfree(glue);

	return 0;
}

#ifdef CONFIG_PM
static void ti81xx_save_context(struct ti81xx_glue *glue)
{
	struct ti81xx_usbss_regs *usbss = &glue->usbss_regs;
	u8 i, j;

	/* save USBSS register */
	usbss->irq_en_set = usbss_read(USBSS_IRQ_ENABLE_SET);

#ifdef CONFIG_USB_TI_CPPI41_DMA
	for (i = 0 ; i < 4 ; i++) {
		usbss->irq_dma_th_tx0[i] =
			usbss_read(USBSS_IRQ_DMA_THRESHOLD_TX0 + (0x4 * i));
		usbss->irq_dma_th_rx0[i] =
			usbss_read(USBSS_IRQ_DMA_THRESHOLD_RX0 + (0x4 * i));
		usbss->irq_dma_th_tx1[i] =
			usbss_read(USBSS_IRQ_DMA_THRESHOLD_TX1 + (0x4 * i));
		usbss->irq_dma_th_rx1[i] =
			usbss_read(USBSS_IRQ_DMA_THRESHOLD_RX1 + (0x4 * i));

		usbss->irq_frame_th_tx0[i] =
			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_TX0 + (0x4 * i));
		usbss->irq_frame_th_rx0[i] =
			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_RX0 + (0x4 * i));
		usbss->irq_frame_th_tx1[i] =
			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_TX1 + (0x4 * i));
		usbss->irq_frame_th_rx1[i] =
			usbss_read(USBSS_IRQ_FRAME_THRESHOLD_RX1 + (0x4 * i));
	}
	for (i = 0 ; i < 2 ; i++) {
		usbss->irq_dma_en[i] =
			usbss_read(USBSS_IRQ_DMA_ENABLE_0 + (0x4 * i));
		usbss->irq_frame_en[i] =
			usbss_read(USBSS_IRQ_FRAME_ENABLE_0 + (0x4 * i));
	}
#endif
	/* save usbX register */
	for (i = 0 ; i < 2 ; i++) {
		struct ti81xx_usb_regs *usb = &glue->usb_regs[i];
		struct musb *musb = platform_get_drvdata(glue->musb[i]);
		void __iomem *cbase = musb->ctrl_base;

		/* disable the timers */
		if (timer_pending(&musb->otg_workaround) &&
					is_host_enabled(musb)) {
			del_timer_sync(&musb->otg_workaround);
			musb->en_otgw_timer = 1;
		}

		if (timer_pending(&musb->otg_timer) &&
					is_otg_enabled(musb)) {
			del_timer_sync(&musb->otg_timer);
			musb->en_otg_timer = 1;
		}

		musb_save_context(musb);
		usb->control = musb_readl(cbase, USB_CTRL_REG);

		for (j = 0 ; j < 2 ; j++)
			usb->irq_en_set[j] = musb_readl(cbase,
					USB_IRQ_ENABLE_SET_0 + (0x4 * j));
#ifdef CONFIG_USB_TI_CPPI41_DMA
		usb->tx_mode = musb_readl(cbase, USB_TX_MODE_REG);
		usb->rx_mode = musb_readl(cbase, USB_RX_MODE_REG);

		for (j = 0 ; j < 15 ; j++)
			usb->grndis_size[j] = musb_readl(cbase,
					USB_GENERIC_RNDIS_EP_SIZE_REG(j + 1));

		usb->auto_req = musb_readl(cbase, TI81XX_USB_AUTOREQ_REG);
		usb->teardn = musb_readl(cbase, TI81XX_USB_TEARDOWN_REG);
		usb->th_xdma_idle = musb_readl(cbase, USB_TH_XDMA_IDLE_REG);
#endif
		usb->srp_fix = musb_readl(cbase, USB_SRP_FIX_TIME_REG);
		usb->phy_utmi = musb_readl(cbase, USB_PHY_UTMI_REG);
		usb->mgc_utmi_loopback = musb_readl(cbase, USB_PHY_UTMI_LB_REG);
		usb->mode = musb_readl(cbase, USB_MODE_REG);
	}
#ifdef CONFIG_USB_TI_CPPI41_DMA
	/* save CPPI4.1 DMA register for dma block 0 */
	cppi41_save_context(0);
#endif
}
static void ti81xx_restore_context(struct ti81xx_glue *glue)
{
	struct ti81xx_usbss_regs *usbss = &glue->usbss_regs;
	u8 i, j;

	/* restore USBSS register */
	usbss_write(USBSS_IRQ_ENABLE_SET, usbss->irq_en_set);

#ifdef CONFIG_USB_TI_CPPI41_DMA
	for (i = 0 ; i < 4 ; i++) {
		usbss_write(USBSS_IRQ_DMA_THRESHOLD_TX0 + (0x4 * i),
				usbss->irq_dma_th_tx0[i]);
		usbss_write(USBSS_IRQ_DMA_THRESHOLD_RX0 + (0x4 * i),
				usbss->irq_dma_th_rx0[i]);
		usbss_write(USBSS_IRQ_DMA_THRESHOLD_TX1 + (0x4 * i),
				usbss->irq_dma_th_tx1[i]);
		usbss_write(USBSS_IRQ_DMA_THRESHOLD_RX1 + (0x4 * i),
				usbss->irq_dma_th_rx1[i]);

		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_TX0 + (0x4 * i),
				usbss->irq_frame_th_tx0[i]);
		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_RX0 + (0x4 * i),
				usbss->irq_frame_th_rx0[i]);
		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_TX1 + (0x4 * i),
				usbss->irq_frame_th_tx1[i]);
		usbss_write(USBSS_IRQ_FRAME_THRESHOLD_RX1 + (0x4 * i),
				usbss->irq_frame_th_rx1[i]);
	}
	for (i = 0 ; i < 2 ; i++) {
		usbss_write(USBSS_IRQ_DMA_ENABLE_0 + (0x4 * i),
				usbss->irq_dma_en[i]);
		usbss_write(USBSS_IRQ_FRAME_ENABLE_0 + (0x4 * i),
				usbss->irq_frame_en[i]);
	}
#endif
	/* restore usbX register */
	for (i = 0 ; i < 2 ; i++) {
		struct ti81xx_usb_regs *usb = &glue->usb_regs[i];
		struct musb *musb = platform_get_drvdata(glue->musb[i]);
		void __iomem *cbase = musb->ctrl_base;

		musb_restore_context(musb);
		musb_writel(cbase, USB_CTRL_REG, usb->control);

		for (j = 0 ; j < 2 ; j++)
			musb_writel(cbase, USB_IRQ_ENABLE_SET_0 + (0x4 * j),
					usb->irq_en_set[j]);

#ifdef CONFIG_USB_TI_CPPI41_DMA
		musb_writel(cbase, USB_TX_MODE_REG, usb->tx_mode);
		musb_writel(cbase, USB_RX_MODE_REG, usb->rx_mode);

		for (j = 0 ; j < 15 ; j++)
			musb_writel(cbase, USB_GENERIC_RNDIS_EP_SIZE_REG(j + 1),
					usb->grndis_size[j]);

		musb_writel(cbase, TI81XX_USB_AUTOREQ_REG, usb->auto_req);
		musb_writel(cbase, TI81XX_USB_TEARDOWN_REG, usb->teardn);
		musb_writel(cbase, USB_TH_XDMA_IDLE_REG, usb->th_xdma_idle);
#endif
		musb_writel(cbase, USB_SRP_FIX_TIME_REG, usb->srp_fix);
		musb_writel(cbase, USB_PHY_UTMI_REG, usb->phy_utmi);
		musb_writel(cbase, USB_PHY_UTMI_LB_REG, usb->mgc_utmi_loopback);
		musb_writel(cbase, USB_MODE_REG, usb->mode);

		/* reenable the timers */
		if (musb->en_otgw_timer && is_host_enabled(musb)) {
			mod_timer(&musb->otg_workaround,
					jiffies + POLL_SECONDS * HZ);
			musb->en_otgw_timer = 0;
		}
		if (musb->en_otg_timer && is_otg_enabled(musb)) {
			mod_timer(&musb->otg_timer,
					jiffies + POLL_SECONDS * HZ);
			musb->en_otg_timer = 0;
		}
	}
#ifdef CONFIG_USB_TI_CPPI41_DMA
	/* restore CPPI4.1 DMA register for dma block 0 */
	cppi41_restore_context(0, dma_sched_table);
#endif
	/* controller needs delay for successful resume */
	msleep(200);
}
static int ti81xx_runtime_suspend(struct device *dev)
{
	struct ti81xx_glue *glue = dev_get_drvdata(dev);
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	struct platform_device *pdev;
	int i;

	if (data->get_context_loss_count)
		glue->context_loss_cnt =
				data->get_context_loss_count(glue->dev);

	/* save wrappers and cppi4.1 dma register */
	ti81xx_save_context(glue);

	/* Shutdown the on-chip PHY and its PLL.
	 * Enable USB PHYWKUP only if enabled through sysfs.
	 * By default USB PHYWKUP is  disabled
	 */
	if (data->set_phy_power) {
		for (i = 0; i <= data->instances; ++i) {
			pdev = glue->musb[i];
			if (device_may_wakeup(&pdev->dev))
				data->set_phy_power(i, 0, true);
			else
				data->set_phy_power(i, 0, false);
		}
	}

	return 0;
}

static int ti81xx_runtime_resume(struct device *dev)
{
	struct ti81xx_glue *glue = dev_get_drvdata(dev);
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	int i, loss_cnt;

	/*
	 * ignore first call of resume as all registers are not yet
	 * initialized
	 */
	if (glue->first) {
		glue->first = 0;
		return 0;
	}

	/* Start the on-chip PHY and its PLL. */
	for (i = 0; i <= data->instances; ++i) {
		if (data->set_phy_power)
			data->set_phy_power(i, 1, false);
	}

	if (data->get_context_loss_count) {
		loss_cnt = data->get_context_loss_count(glue->dev);
		if (loss_cnt < 0) {
			dev_err(dev, "%s failed, countext loss count = %d\n",
					__func__, loss_cnt);
		} else if (glue->context_loss_cnt == loss_cnt) {
			return 0;
		}
	}

	/* restore wrappers and cppi4.1 dma register */
	ti81xx_restore_context(glue);

	return 0;
}

static const struct dev_pm_ops ti81xx_pm_ops = {
	.runtime_suspend = ti81xx_runtime_suspend,
	.runtime_resume	= ti81xx_runtime_resume,
};

#define DEV_PM_OPS	(&ti81xx_pm_ops)
#else
#define DEV_PM_OPS	NULL
#endif

static struct platform_driver ti81xx_musb_driver = {
	.remove         = __exit_p(ti81xx_remove),
	.driver         = {
		.name   = "musb-ti81xx",
		.pm	= DEV_PM_OPS,
	},
};

MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
MODULE_LICENSE("GPL v2");

static int __init ti81xx_glue_init(void)
{
	return platform_driver_probe(&ti81xx_musb_driver, ti81xx_probe);
}
subsys_initcall(ti81xx_glue_init);

static void __exit ti81xx_glue_exit(void)
{
#ifdef CONFIG_USB_TI_CPPI41_DMA
	/* free the usbss irq */
	free_irq(TI81XX_IRQ_USBSS, 0);
#endif

	/* disable the interrupts */
	usbss_write(USBSS_IRQ_EOI, 0);
	usbss_write(USBSS_IRQ_ENABLE_SET, 0);
	usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0);

	/* unregister platform driver */
	platform_driver_unregister(&ti81xx_musb_driver);
}
module_exit(ti81xx_glue_exit);

0 Bin Liu over 8 years ago in reply to Shabtai Haim

TI__Guru*** 125156 points

In your version of ti81xx.c,

  1080         if (usbintr)
  1081                 musb_writel(reg_base, USB_CORE_INTR_STATUS_REG, usbintr);
  1082         musb->int_usb = (usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
  1083                                 
  1084         //dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);
  1085 
  1086         if (musb->int_usb & MUSB_INTR_SOF) {

You have line #1084 commented out, that is why your log does not have the message that I was looking for. Please uncomment it and re-capture the log until the issue happens.

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Hi Bin,

Sorry about the longs delay in responding your questions, I will try to help to push this case forward.

I did what you asked (dynamic print) , attached is the file with logs, it is full with prints such as

"musb-hdrc musb-hdrc.1: usbintr (0) epintr(4000000)"

I also added to the top of the file the boot messages , just in case you would like to see themmusb.txt

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Elison,

Thanks for uploading the log, it shows the ep interrupt 0x4000000 flooding which overflows the dmesg buffer, so we lost the log information at the beginning of the failure.

Please try the following to capture the log differently. Instead of "echo 'func ti81xx_interrupt =p' > ..." as we did to capture the log, can you please apply the follwing patch to capture the usb interrupt log?

diff --git a/drivers/usb/musb/ti81xx.c b/drivers/usb/musb/ti81xx.c
index 077f6ec..b16519f 100644
--- a/drivers/usb/musb/ti81xx.c
+++ b/drivers/usb/musb/ti81xx.c
@@ -1049,6 +1049,7 @@ static irqreturn_t ti81xx_interrupt(int irq, void *hci)
        musb->int_usb = (usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
 
        dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);
+       dev_err(musb->controller, "usbintr (%x)", usbintr);
 
        if (musb->int_usb & MUSB_INTR_SOF) {
                if (musb->sof_enabled) {

0 Bin Liu over 8 years ago in reply to Bin Liu

TI__Guru*** 125156 points

Please use this patch instead to capture the log.

diff --git a/drivers/usb/musb/ti81xx.c b/drivers/usb/musb/ti81xx.c
index 077f6ec..47fbba7 100644
--- a/drivers/usb/musb/ti81xx.c
+++ b/drivers/usb/musb/ti81xx.c
@@ -1044,8 +1044,11 @@ static irqreturn_t ti81xx_interrupt(int irq, void *hci)
                goto eoi;
        }
 
-       if (usbintr)
+       if (usbintr) {
                musb_writel(reg_base, USB_CORE_INTR_STATUS_REG, usbintr);
+               dev_err(musb->controller, "usbintr (%x)", usbintr);
+       }
+
        musb->int_usb = (usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
 
        dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

/ #
/ # dmesg
[    0.000000] Linux version 3.2.0 (bee031@srv608) (gcc version 4.7.3 (Buildroot 2014.05) ) #2 Sun Sep 20 14:12:45 IST 2015
[    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] Machine: AM335x Prince Kernel - Prince_SCM_I00.0042 - (bee031@srv608)
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] On node 0 totalpages: 65536
[    0.000000] free_area_init_node: node 0, pgdat c056dcf4, node_mem_map c05a2000
[    0.000000]   Normal zone: 512 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 65024 pages, LIFO batch:15
[    0.000000] AM335X ES2.1 (neon )
[    0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[    0.000000] pcpu-alloc: [0] 0
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 65024
[    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/mtdblock10 rootfstype=cramfs rootwait=1 eth=fc:0a:81:c8:c8:e9 mod=M modem_type=4G
[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Memory: 256MB = 256MB total
[    0.000000] Memory: 254088k/254088k available, 8056k reserved, 0K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xd0800000 - 0xff000000   ( 744 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
[    0.000000]     modules : 0xbf000000 - 0xc0000000   (  16 MB)
[    0.000000]       .text : 0xc0008000 - 0xc04e6000   (4984 kB)
[    0.000000]       .init : 0xc04e6000 - 0xc051b000   ( 212 kB)
[    0.000000]       .data : 0xc051c000 - 0xc0576ba8   ( 363 kB)
[    0.000000]        .bss : 0xc0576bcc - 0xc05a1838   ( 172 kB)
[    0.000000] NR_IRQS:396
[    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts
[    0.000000] Total of 128 interrupts on 1 active controller
[    0.000000] OMAP clockevent source: GPTIMER2 at 24000000 Hz
[    0.000000] omap_dm_timer_switch_src: Switching to HW default clocksource(sys_clkin_ck) for timer1, this may impact timekeeping in low power state
[    0.000000] OMAP clocksource: GPTIMER1 at 24000000 Hz
[    0.000000] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms
[    0.000000] Console: colour dummy device 80x30
[    0.000207] Calibrating delay loop... 718.02 BogoMIPS (lpj=3590144)
[    0.117198] pid_max: default: 32768 minimum: 301
[    0.117322] Security Framework initialized
[    0.117428] Mount-cache hash table entries: 512
[    0.117850] CPU: Testing write buffer coherency: ok
[    0.118678] devtmpfs: initialized
[    0.138748] omap_hwmod: pruss: failed to hardreset
[    0.139979] print_constraints: dummy:
[    0.140369] NET: Registered protocol family 16
[    0.142625] OMAP GPIO hardware version 0.1
[    0.145119] omap_mux_init: Add partition: #1: core, flags: 0
[    0.147049]  omap_i2c.1: alias fck already exists
[    0.147401]  omap_i2c.2: alias fck already exists
[    0.147607] The board is IMOD_SCM
[    0.148879] am335x_imod_setup_mac_addr: "ethaddr" parsed from command line: fc:0a:81:c8:c8:e9
[    0.148906] am335x_imod_setup_mac_addr: "ethaddr" saved in "mac_addr0": fc:a:81:c8:c8:e9
[    0.148921] am335x_imod_setup_mac_addr: saved in "mac_addr1": fc:a:81:c8:c8:ea
[    0.148934] am335x_imod_setup_mac_addr: saved in "mac_addr2": fc:a:81:c8:c8:eb
[    0.149725]  omap2_mcspi.1: alias fck already exists
[    0.149946]  omap2_mcspi.2: alias fck already exists
[    0.150893]  edma.0: alias fck already exists
[    0.150913]  edma.0: alias fck already exists
[    0.150931]  edma.0: alias fck already exists
[    0.169736] bio: create slab <bio-0> at 0
[    0.171153] CPCAP init started
[    0.171439] CPCAP probe started
[    0.171669] CPCAP get voltage
[    0.171685] print_constraints: vdd_mpu: 912 <--> 1362 mV normal
[    0.171971] CPCAP get voltage
[    0.171983] print_constraints: vdd_core: 912 <--> 1137 mV normal
[    0.172228] CPCAP get voltage
[    0.172240] print_constraints: vmmc: normal
[    0.172479] CPCAP get voltage
[    0.172490] print_constraints: vmmc_aux: normal
[    0.172601] CPCAP get voltage
[    0.172612] am335x_opp_update: physical regulator not present for core(-1)
[    0.172663] CPCAP probe finished
[    0.172839] CPCAP init finished
[    0.172948] ------------ AZ <omap2_mcspi_probe>:
[    0.173299] ------------ AZ <omap2_mcspi_probe>: success
[    0.173372] ------------ AZ <omap2_mcspi_probe>:
[    0.176356]  cpcap_irq_init <irq:220>
[    0.177729] cpcap_irq_register <42>
[    0.177947] cpcap_irq_register <43>
[    0.178153] CPCAP: <verify_uvlo_data> [0x46]
[    0.178164] >>>> 1wire:  <vr_battery_init_read>
[    0.237198] >>>> 1wire:  <OwSearch> 0x55, 0
[    0.257180] >>>> 1wire: vr_battery_init_read:: battery 1-wire scan/read failed. Devices detected[0]
[    0.257238] CPCAP: battery UNVLO value (reading) == <0x0>
[    0.257250] verify_uvlo_data: battery reading failed <2>, or invalid value received <0x0>, setting default
[    0.257357] cpcap_irq_register <41>
[    0.257413] cpcap_irq_register <40>
[    0.258227] >>>> 1wire: +++++ accy_detach_handler called accy_connected[0],ireg_val[0x81]
[    0.258244] >>>> 1wire: ----- accy_detach_handler caught invalid event accy_connected:<0>,reg:<129>
[    0.258444] initOwInterface: PTT interrupt <225> registered
[    0.258460] >>>> 1wire: accy_cpcap_init: accy disconnected <0>
[    0.258688] ------------ AZ <omap2_mcspi_probe>: success
[    0.259721] usbcore: registered new interface driver usbfs
[    0.260048] usbcore: registered new interface driver hub
[    0.260255] usbcore: registered new device driver usb
[    0.260628] registerd cppi-dma Intr @ IRQ 17
[    0.260641] Cppi41 Init Done Qmgr-base(d087a000) dma-base(d0878000)
[    0.260650] Cppi41 Init Done
[    0.260678] musb-ti81xx musb-ti81xx: musb0, board_mode=0x13, plat_mode=0x3
[    0.261011] musb-ti81xx musb-ti81xx: musb1, board_mode=0x13, plat_mode=0x1
[    0.262191] omap_i2c omap_i2c.1: bus 1 rev2.4.0 at 100 kHz
[    0.277208] omap_i2c omap_i2c.2: bus 2 rev2.4.0 at 100 kHz
[    0.278777] Advanced Linux Sound Architecture Driver Version 1.0.24.
[    0.279569] Switching to clocksource gp timer
[    0.298342] musb-hdrc: version 6.0, ?dma?, otg (peripheral+host)
[    0.298573] musb-hdrc musb-hdrc.0: dma type: dma-cppi41
[    0.298924] MUSB0 controller's USBSS revision = 4ea20800
[    0.298948] TxFifo Empty intr disabled
[    0.298958] musb0: Enabled SW babble control
[    0.299337] musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn)
[    0.299356] musb-hdrc: MHDRC RTL version 2.0
[    0.299367] musb-hdrc: setup fifo_mode 4
[    0.299398] musb-hdrc: 28/31 max ep, 16384/16384 memory
[    0.299414] musb-hdrc.0: bulk split disabled
[    0.299422] musb-hdrc.0: bulk combine disabled
[    0.300102] musb-hdrc musb-hdrc.0: USB OTG mode controller at d083c000 using DMA, IRQ 18
[    0.300281] musb-hdrc musb-hdrc.1: dma type: dma-cppi41
[    0.300625] MUSB1 controller's USBSS revision = 4ea20800
[    0.300643] TxFifo Empty intr disabled
[    0.300652] musb1: Enabled SW babble control
[    0.301009] musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn)
[    0.301026] musb-hdrc: MHDRC RTL version 2.0
[    0.301035] musb-hdrc: setup fifo_mode 4
[    0.301063] musb-hdrc: 28/31 max ep, 16384/16384 memory
[    0.301077] musb-hdrc.1: bulk split disabled
[    0.301085] musb-hdrc.1: bulk combine disabled
[    0.301163] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
[    0.301276] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
[    0.301427] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    0.301442] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    0.301455] usb usb1: Product: MUSB HDRC host driver
[    0.301465] usb usb1: Manufacturer: Linux 3.2.0 musb-hcd
[    0.301475] usb usb1: SerialNumber: musb-hdrc.1
[    0.302507] hub 1-0:1.0: USB hub found
[    0.302542] hub 1-0:1.0: 1 port detected
[    0.303176] musb-hdrc musb-hdrc.1: USB Host mode controller at d083e800 using DMA, IRQ 19
[    0.303641] NET: Registered protocol family 2
[    0.303850] IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.304179] TCP established hash table entries: 8192 (order: 4, 65536 bytes)
[    0.304339] TCP bind hash table entries: 8192 (order: 3, 32768 bytes)
[    0.304433] TCP: Hash tables configured (established 8192 bind 8192)
[    0.304446] TCP reno registered
[    0.304458] UDP hash table entries: 256 (order: 0, 4096 bytes)
[    0.304481] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[    0.304681] NET: Registered protocol family 1
[    0.304943] RPC: Registered named UNIX socket transport module.
[    0.304955] RPC: Registered udp transport module.
[    0.304963] RPC: Registered tcp transport module.
[    0.304972] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.305206] NetWinder Floating Point Emulator V0.97 (double precision)
[    0.305433] omap-gpmc omap-gpmc: GPMC revision 6.0
[    0.305447] Registering NAND on CS1
[    0.318888] VFS: Disk quotas dquot_6.5.2
[    0.318958] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    0.319535] JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[    0.319834] msgmni has been set to 496
[    0.323295] alg: No test for stdrng (krng)
[    0.324143] io scheduler noop registered
[    0.324156] io scheduler deadline registered
[    0.324237] io scheduler cfq registered (default)
[    0.325435] omap_uart.0: ttyO0 at MMIO 0x44e09000 (irq = 72) is a OMAP UART0
[    1.105468] musb-hdrc musb-hdrc.1: !!!!!!!!!!!  usbintr (100)
[    1.111503] console [ttyO0] enabled
[    1.115910] omap_uart.1: ttyO1 at MMIO 0x48022000 (irq = 73) is a OMAP UART1
[    1.123876] omap_uart.2: ttyO2 at MMIO 0x48024000 (irq = 74) is a OMAP UART2
[    1.131775] omap_uart.3: ttyO3 at MMIO 0x481a6000 (irq = 44) is a OMAP UART3
[    1.139644] omap_uart.4: ttyO4 at MMIO 0x481a8000 (irq = 45) is a OMAP UART4
[    1.147501] omap_uart.5: ttyO5 at MMIO 0x481aa000 (irq = 46) is a OMAP UART5
[    1.155945] omap4_rng omap4_rng: OMAP4 Random Number Generator ver. 2.00
[    1.163866] brd: module loaded
[    1.172584] loop: module loaded
[    1.177763] mtdoops: mtd device (mtddev=name/number) must be supplied
[    1.184928] omap2-nand driver initializing
[    1.189526] ONFI flash detected
[    1.192958] ONFI param page 0 valid
[    1.196602] NAND device: Manufacturer ID: 0x2c, Chip ID: 0xaa (Micron MT29F2G08ABBEAH4)
[    1.205194] Creating 12 MTD partitions on "omap2-nand.0":
[    1.210858] 0x000000000000-0x000000020000 : "Reserved1"
[    1.217904] 0x000000020000-0x000000040000 : "TestResults"
[    1.225006] 0x000000040000-0x000000060000 : "Reserved2"
[    1.231851] 0x000000060000-0x000000080000 : "Reserved3"
[    1.238682] 0x000000080000-0x000000260000 : "u-boot"
[    1.246108] 0x000000260000-0x000000280000 : "u-boot-env"
[    1.253100] 0x000000280000-0x000000780000 : "kernel"
[    1.261792] 0x000000780000-0x000000a80000 : "LOGS_ON_OFF"
[    1.270060] 0x000000a80000-0x000000f80000 : "LOGS_USER"
[    1.278883] 0x000000f80000-0x000001b80000 : "LOGS_SYSTEM"
[    1.290863] 0x000001b80000-0x000005b80000 : "rootfs"
[    1.323906] 0x000005b80000-0x000010000000 : "NandTest"
[    1.398902] OneNAND driver initializing
[    1.404500] usbcore: registered new interface driver cdc_ether
[    1.410887] usbcore: registered new interface driver cdc_acm
[    1.416784] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
[    1.425517] usbcore: registered new interface driver usbserial
[    1.431617] usbserial: USB Serial Driver core
[    1.436313] USB Serial support registered for GSM modem (1-port)
[    1.442869] usbcore: registered new interface driver option
[    1.448678] option: v0.7.2:USB Driver for GSM modems
[    1.454240] mousedev: PS/2 mouse device common for all mice
[    1.460872] cpcap_rtc cpcap_rtc: rtc core: registered cpcap_rtc as rtc0
[    1.468231] i2c /dev entries driver
[    1.490727] OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
[    1.497298] CPCAP get voltage
[    1.498760] cpuidle: using governor ladder
[    1.504038] cpuidle: using governor menu
[    1.508757] omap4_aes_mod_init: loading AM33X AES driver
[    1.514437] omap4-aes omap4-aes: AM33X AES hw accel rev: 3.02
[    1.520958] omap4_aes_probe: probe() done
[    1.525380] omap4_sham_mod_init: loading AM33X SHA/MD5 driver
[    1.531532] omap4-sham omap4-sham: AM33X SHA/MD5 hw accel rev: 4.03
[    1.543157] omap4_sham_probe: probe() done
[    1.549688] ALSA device list:
[    1.552786]   No soundcards found.
[    1.556326] oprofile: hardware counters not available
[    1.561600] oprofile: using timer interrupt.
[    1.566089] nf_conntrack version 0.5.0 (3970 buckets, 15880 max)
[    1.572899] ip_tables: (C) 2000-2006 Netfilter Core Team
[    1.578563] TCP cubic registered
[    1.581971] NET: Registered protocol family 17
[    1.586722] Bridge firewalling registered
[    1.590967] 8021q: 802.1Q VLAN Support v1.8
[    1.595347] Registering the dns_resolver key type
[    1.600308] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
[    1.608302] ThumbEE CPU extension supported.
[    1.612833] mux: Failed to setup hwmod io irq -22
[    1.618478] Power Management for AM33XX family
[    1.623378] Trying to load am335x-pm-firmware.bin (60 secs timeout)
[    1.630058] Copied the M3 firmware to UMEM
[    1.634409] Cortex M3 Firmware Version = 0x181
[    1.642852] clock: disabling unused clocks to save power
[    1.648748] CPCAP get voltage
[    1.648770] CPCAP set voltage
[    1.661367] cpcap_rtc cpcap_rtc: setting system clock to 1970-01-01 01:39:13 UTC (5953)
[    1.675230] VFS: Mounted root (cramfs filesystem) readonly on device 31:10.
[    1.682690] devtmpfs: mounted
[    1.686141] Freeing init memory: 212K
[    2.434933]  gadget: using random self ethernet address
[    2.453222] usb0: MAC 16:73:96:9f:f5:01
[    2.457260] usb0: HOST MAC 00:16:08:02:99:d7
[    2.461894]  gadget: using random self ethernet address
[    2.468831] usb1: MAC 16:ec:4b:4f:53:59
[    2.472912] usb1: HOST MAC 00:16:08:02:99:d8
[    2.477449]  gadget: using random self ethernet address
[    2.482936]  gadget: using random host ethernet address
[    2.501679] usb2: MAC 6e:65:0c:19:96:38
[    2.505718] usb2: HOST MAC 4a:31:8b:da:31:90
[    2.511665]  gadget: Eilon, version: Eilon SQN emulation1
[    2.517346]  gadget: g_cdc ready
[    2.520795] musb-hdrc musb-hdrc.0: MUSB HDRC host driver
[    2.526417] musb-hdrc musb-hdrc.0: new USB bus registered, assigned bus number 2
[    2.534304] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
[    2.541429] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.548987] usb usb2: Product: MUSB HDRC host driver
[    2.554198] usb usb2: Manufacturer: Linux 3.2.0 musb-hcd
[    2.559763] usb usb2: SerialNumber: musb-hdrc.0
[    2.578501] hub 2-0:1.0: USB hub found
[    2.582573] hub 2-0:1.0: 1 port detected
[    2.649035] musb-hdrc musb-hdrc.0: !!!!!!!!!!!  usbintr (1)
[    2.791305] musb-hdrc musb-hdrc.0: !!!!!!!!!!!  usbintr (4)
[    2.810144] Disabling lock debugging due to kernel taint
[    2.824984]
[    2.824993] --- Starting IMOD Configuration unit ...
[    2.832344] *
[    2.832347] IMOD config module - Prince_SCM_I00.0042 - (bee031@srv608) (Sep 20 2015 14:12:50)
[    2.844320] * Initializing IMOD Configuration module ...
[    2.851265] * Initializing GPIO driver
[    2.860106] * Initializing User-space character device driver
[    2.914661] musb-hdrc musb-hdrc.0: !!!!!!!!!!!  usbintr (4)
[    2.921345] * Initializing MSP430 driver
[    2.925460] MSP modoule Install
[    2.925464]
[    2.946732] MSP modoule device client OK :msp430_i2c_client=cf0b6800
[    2.946742]
[    2.962783] MSP modoule client check alive OK !
[    2.962794]
[    2.969122] --- IMOD Configuration is ON!
[    2.969126]
[    3.082623]  gadget: high-speed config #1: CDC Composite (3*ECM + ACM)
[    3.989786] CPCAP get voltage
[    3.989931] CPCAP set voltage
[    4.077466] Function: "IMOD_CharDev_IOCTL" called!
[    4.084412] CPCAP get voltage
[    4.084448] CPCAP set voltage
[    4.121421] MSP modoule Open
[    4.121436]
[    4.126421] OW_down opened
[    4.131190] OW_up opened
[    4.135888] >>>> 1wire: OW ow_dev_read ow_param:<0x5>
[    4.141854] MSP modoule IOCTL
[    4.141864]
[    4.147414] Case IMOD_MSP430_Status IOCTL
[    4.147419]
[    4.154576] MSP modoule IMOD_MSP430_SendMsg(),539  :
[    4.154582]
[    4.169222] MSP modoule IMOD_MSP430_GetMsg(),484  :
[    4.169231]
[    4.204414] MSP430_INT_FROM_MSP1_PIN_hndl  = 1
[    4.204420]
[    4.211251] MSP modoule IMOD_MSP430_poll_msp430_irq1_pin(),616  :  IRQ1=1.
[    4.211258]
[    4.319675] CPCAP get voltage
[    4.319832] CPCAP set voltage
[    4.410201] MSP modoule IMOD_MSP430_GetMsg(),511  :  i2c_master_recv() Success !
[    4.410227]
[    4.419685] MSP modoule IMOD_MSP430_Status(),791  : STATUS: PowerUp_Reason=255, QuickAction_key=1, Snapshot_key=1,  VERSION=1.09, strVer=DEV Jul  2 2015, HW_ID=2
[    4.419716]
[   17.584671] musb-hdrc musb-hdrc.1: !!!!!!!!!!!  usbintr (10)
[   17.860781] usb 1-1: new high-speed USB device number 2 using musb-hdrc
[   18.101415] usb 1-1: New USB device found, idVendor=258d, idProduct=2000
[   18.108515] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[   18.116098] usb 1-1: Product: SQN
[   18.119605] usb 1-1: Manufacturer: Sequans Communications
[   18.125331] usb 1-1: SerialNumber: 452301081600
[   18.186002] cdc_ether 1-1:1.0: eth0: register 'cdc_ether' at usb-musb-hdrc.1-1, CDC Ethernet Device, 00:16:08:01:23:45
[   18.231203] cdc_acm 1-1:1.2: This device cannot do calls on its own. It is not a modem.
[   18.241075] cdc_acm 1-1:1.2: ttyACM0: USB ACM device
[   18.310364] CPCAP get voltage
[   18.310410] CPCAP set voltage
[   18.323215] device usb0 entered promiscuous mode
[   18.346605] cdc_ether 1-1:1.4: eth1: register 'cdc_ether' at usb-musb-hdrc.1-1, CDC Ethernet Device, 00:16:08:01:23:46
[   18.365399] device eth0 entered promiscuous mode
[   18.384029] br0: port 1(usb0) entering forwarding state
[   18.389568] br0: port 1(usb0) entering forwarding state
[   18.436862] device usb1 entered promiscuous mode
[   18.447639] device eth1 entered promiscuous mode
[   18.462404] br1: port 1(usb1) entering forwarding state
[   18.467986] br1: port 1(usb1) entering forwarding state
[   18.479452] br1: port 2(eth1) entering forwarding state
[   18.485023] br1: port 2(eth1) entering forwarding state
[   19.049746] CPCAP get voltage
[   19.049886] CPCAP set voltage
[   19.329956] br0: port 2(eth0) entering forwarding state
[   19.335595] br0: port 2(eth0) entering forwarding state
[   30.451194]
[   33.399663] br0: port 1(usb0) entering forwarding state
[   33.479648] br1: port 1(usb1) entering forwarding state
[   33.519639] br1: port 2(eth1) entering forwarding state
[   34.359642] br0: port 2(eth0) entering forwarding state
[  111.009014]
[  594.748424]
[  668.462413]
[  720.792437]
[ 1248.780660]

Hi Bin,

I applied the patch you suggested and reproduced the issue. unfortunately there are no relevant logs at the time the issue happens.

Attached is the new log

Thanks,

0 Eilon Eyal74533 over 8 years ago in reply to Eilon Eyal74533

Intellectual 390 points

regdump_musb-hdrc.txt

/ # cat /sys/kernel/debug/musb-hdrc.1/regdump
MUSB (M)HDRC Register Dump
FAddr       : 00
Power       : f0
Frame       : 014b
Index       : 0f
Testmode    : 00
TxMaxPp     : 0000
TxCSRp      : 0000
RxMaxPp     : 0000
RxCSR       : 0000
RxCount     : 0000
ConfigData  : 33
DevCtl      : 5d
MISC        : 44
TxFIFOsz    : 07
RxFIFOsz    : 07
TxFIFOadd   : 0780
RxFIFOadd   : 0780
VControl    : 00000000
HWVers      : 0800
EPInfo      : ff
RAMInfo     : 0d
LinkInfo    : 5c
VPLen       : 3c
HS_EOF1     : 80
FS_EOF1     : 77
LS_EOF1     : 72
SOFT_RST    : 00
DMA_CNTLch0 : 0000
DMA_ADDRch0 : 00000000
DMA_COUNTch0: 00000000
DMA_CNTLch1 : 0000
DMA_ADDRch1 : 00000000
DMA_COUNTch1: 00000000
DMA_CNTLch2 : 0000
DMA_ADDRch2 : 00000000
DMA_COUNTch2: 00000000
DMA_CNTLch3 : 0000
DMA_ADDRch3 : 00000000
DMA_COUNTch3: 00000000
DMA_CNTLch4 : 0000
DMA_ADDRch4 : 00000000
DMA_COUNTch4: 00000000
DMA_CNTLch5 : 0000
DMA_ADDRch5 : 00000000
DMA_COUNTch5: 00000000
DMA_CNTLch6 : 0000
DMA_ADDRch6 : 00000000
DMA_COUNTch6: 00000000
DMA_CNTLch7 : 0000
DMA_ADDRch7 : 00000000
DMA_COUNTch7: 00000000
/ #





/ # cat /sys/kernel/debug/musb-hdrc.0/regdump
MUSB (M)HDRC Register Dump
FAddr       : 02
Power       : f0
Frame       : 0068
Index       : 00
Testmode    : 00
TxMaxPp     : 0000
TxCSRp      : 0000
RxMaxPp     : 0000
RxCSR       : 0000
RxCount     : 0000
ConfigData  : de
DevCtl      : 99
MISC        : 44
TxFIFOsz    : 00
RxFIFOsz    : 00
TxFIFOadd   : 0000
RxFIFOadd   : 0000
VControl    : 00000000
HWVers      : 0800
EPInfo      : ff
RAMInfo     : 0d
LinkInfo    : 5c
VPLen       : 3c
HS_EOF1     : 80
FS_EOF1     : 77
LS_EOF1     : 72
SOFT_RST    : 00
DMA_CNTLch0 : 0000
DMA_ADDRch0 : 00000000
DMA_COUNTch0: 00000000
DMA_CNTLch1 : 0000
DMA_ADDRch1 : 00000000
DMA_COUNTch1: 00000000
DMA_CNTLch2 : 0000
DMA_ADDRch2 : 00000000
DMA_COUNTch2: 00000000
DMA_CNTLch3 : 0000
DMA_ADDRch3 : 00000000
DMA_COUNTch3: 00000000
DMA_CNTLch4 : 0000
DMA_ADDRch4 : 00000000
DMA_COUNTch4: 00000000
DMA_CNTLch5 : 0000
DMA_ADDRch5 : 00000000
DMA_COUNTch5: 00000000
DMA_CNTLch6 : 0000
DMA_ADDRch6 : 00000000
DMA_COUNTch6: 00000000
DMA_CNTLch7 : 0000
DMA_ADDRch7 : 00000000
DMA_COUNTch7: 00000000

and also here is the regdump capture of both USB controllers

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

Is the regdump above captured before or after the issue happened? Comparing the value to that in your first post, it seems to be captured before the issue happened. If so please capture the regdump after the issue happened.

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Hi Bin,
The regdump was captured after the issue happened .
since the first dump was captured a while ago I think it would be better to ignore the first regdump and only look at the last one I provided .

Thanks,

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

The dmesg log show both USB ports are used, and the register log shows USB1 port seems to ok in host mode and has a device enumerated, and USB0 port seems to be in device mode, but I thought your modem is connected on USB0 port from the information you provided before.

The issue has been last for months, but still misses some information for me to understand your use case, so please provide the following information.

- USB0 port works in host-only mode, right? Is the modem connected to USB0 port? If not, what device is on USB0 port?
- USB1 port is in host-only or otg mode? What device is connected to?
- Please share your USB portion of the schematics;
- When the issue happens, please capture *both* the register dump and log of 'cat /proc/driver/musb-hdrc.X'.

0 Eilon Eyal74533 over 8 years ago in reply to Eilon Eyal74533

Intellectual 390 points

Hi Bin,
please let me clarify and further explain about our product .

Our product is built from 3 main components
1. A 4G usb modem, its USB rule is peripheral
2. Sitara board runing linux (one side is a USB host the other is peripheral)
3. Qualcomm MSM8974 running Android (the MSM8974 modem is disabled) (the usb rule is host only)

The 4G modem connected to the Sitara musb-hdrc.1 . the modem is peripheral and the Sitara Host. Mode=Host, OTG state: a_host; active
The modem enumerate 2 CDC-ECM + 1 CDC-ACM

Sitara musb-hdrc.0 is connected to the QCOM cpu and its rule is peripheral Mode=Peripheral OTG state: b_peripheral; active
A gadget composite driver is bind to this usb port and it enumerate 3 CDC-ECM + 1 CDC-ACM to the QCOM CPU.
1 CDC-ECM is used for internal QCOM <-> Sitara communication
for the other 2 ECM network interfaces we use ip bridge (brctl) to simple pass all IP communication from the QCOM to the modem.
for the ACM we use socat to pass the traffic from QCOM to the modem

during the case we describe when DMA is active, 1 of the data interfaces which is bridged simply stop working, the other interfaces works ok. When we use PIO everything works OK during very long stress tests .

I am working with HW team to produce the HW schematics relevant to the USB part.

Thanks,

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

Thanks for the clarification. It helps on understanding the use case. We have been focusing on the wrong direction because of the logs/descriptions provided earlier.

Since the USB traffic runs cross both MUSB ports on AM335x, have you isolated the issue is in MUSB0 peripheral port or MUSB1 host port? You probably need USB protocol analyzer to help the isolation.

BTY, please also try the the following path to see if it affects anything.

diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 3f24c05..5544a55 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -1959,7 +1959,7 @@ static int musb_schedule(
        best_diff = 4096;
        best_end = -1;
 
-       for (epnum = 1, hw_ep = musb->endpoints + 1;
+       for (epnum = is_in ? 1 : 6, hw_ep = musb->endpoints + epnum;
                        epnum < musb->nr_endpoints;
                        epnum++, hw_ep++) {
                int     diff;

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Hi Bin
first I would like to thank you for your time patient (I know it is lasting for a long time)

the issue Always happens on musb-hdrc.0 which is as I wrote above in peripheral mode and is connected to the QCOM CPU.
some additional information.
1. The issue always happens on a single interface while the other (other 2 ECM and 1 ACM) works OK.
2. since It is a ECM interface. After the error condition happens I stop the application on the QCOM CPU which initiate the IP traffic and then I do Ping from QCOM to the Sitara while doing TCPDUMP on the sitara. I can see that I receive the icmp echo request and reply them back, but it seems that the QCOM CPU does not receive them.
3. the traffic going through the bad interface is RTP (audio+Video) which are a high stream of small packets.

in addition I applied your patch from above and will let you know if it helps.

Thanks

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

Can you put a USB protocol analyzer on the MUSB0 port to capture a trace until the issue happens? I 'd like to check if there is any specific data pattern which could cause CPPI lockup.

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Hi Bin,

I am afraid the the USB bus is on the PCB and we cannot put an external analyzer . can you guide me were I can put printk's to provide the needed info?

I am able to reproduce the issue now very fast so there will not be a lot of logs

Thanks,

0 Eilon Eyal74533 over 8 years ago in reply to Eilon Eyal74533

Intellectual 390 points

Hi Bin,

our hardware team managed to connect the USB into an analyzer. but The Ellisys file is bigger than the size permitted . is there a way to attach 46K file?

Thanks,

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

Please following the instruction below to upload the trace. Please note on step 7 for uploading 'done.now' file.
===============
The ftp dropoff directory 'kachith' was created on 10/26/2015 08:30:01.

The ftp dropoff directory is a write only directory. Files copied to the dropoff directory cannot be viewed or downloaded. The files will be moved to a pickup area when a file called "done.now" is copied to the dropoff directory or after 48 hours. The dropoff directory will not be available after that time.

To copy files to the dropoff directory:

1. Open an ftp session to ftpdrop.ti.com.
ftp ftpdrop.ti.com

2. Login with the userid 'anonymous'.
Name: anonymous

3. Use your email address for the password.

4. Change directories to the dropoff directory.
ftp> cd /pub/share/kachith

Note: If you are using a graphical ftp client, you will not
see the hidden dropoff directory name kachith appear
in the file list. You will need to use a manual
'Change Directory' or 'CD' command to change into the
dropoff directory.

5. Set the file transfer mode to ascii or binary as necessary.
ftp> bin

6. Transfer the file.
ftp> put <file>

7. Create a file on your local system called "done.now" and copy the
file to the dropoff directory. This is used to indicate that the
files in the dropoff directory can now be moved to the pickup area.
If this file is not copied to the dropoff directory then you will
have to wait 48 hours before the files are moved to the pickkup area.
ftp> put done.now

8. End the ftp session.
ftp> quit

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Thanks Bin for the detailed instructions. I placed a file called untitled.zip inside the ftp directory. inside this file there is file called untitled.ufo which is Ellisys format.

you can download the viewer from "http://www.ellisys.com/products/download/visualusb.msi"

the issue we see is on EP3 IN, you can filter on EP3 and IN. please let me know if you see anything on your side.

Thanks a lot for all the help

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Sorry for previous confusion the issue happens on EP1 IN and NOT on EP3 as I previously wrote

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

Thanks for uploading the traces.

Please bear with me as I never used Ellisys tools before, and its UI is very difficult for me. I don't have a conclusion yet, but please see the attached screenshot of Untitied.ufo trace.

I am unable to find the option to switch to transfer view, so I assume each IN transfer on EP1 contains 3 transactions with data size 512, 512, and 117 bytes respectively. Please check the highlights in the screenshot, for the very last IN transfer, the 117-byte transaction is received 8+ ms after the 2nd 512-byte transaction, then the device is no longer sending data for 16 seconds until the end of the trace.

I am not sure why the device stop sending data after the last transfer, also I am wondering if the last IN transfer which has 8+ms delay would cause any issue in the network layer.

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Hi Bin,

I could not find the way to view an attached file. could you please let me know how to do it?

as for what you see. please make sure you allow the viewer to present the NACKs by default it would not so you miss the last part of the communication. you can do that by pressing right button and in filter sub menu choose to display NACKs

Thanks

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon, sorry I forgot to attach the file. I've corrected my previous post, please check the screenshot again.

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Hi Bin,
when I cat /proc/driver/musb_hdrc.0 before the issue I can see that
ep1in (hw1): 1buf dma, csr 2404 maxp 0200
TX DMA0: 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
(queue empty)

after the the issue (this never changes after the issue):
ep1in (hw1): 1buf dma, csr 3404 maxp 0200
TX DMA0: 00000000 00000000, 00000000 00000000; 00000000 00000000 00000000 .. 00000000
req cf4ea590, -820920080/-814664192
req cf4ea5d0, -820920080/-815457472
req cf4ea610, -820920080/-815380992
req cf4ea550, -820920080/-815382336
req cf4ea510, -820920080/-814663040
req cf4ea4d0, -820920080/-815073280
req cf4ea490, -820920080/-814664576
req cf4ea650, -820920080/-815390592
req cf4ea690, -820920080/-814665344
req cf4ea6d0, -820920080/-821724800

I think that "tx_complete" is not called for this particular interface and therefore the network is stopped since the TX queue is empty
do you think It would help to prevent ZLP by preventing the request length from being an exact modulo of of the max packet?

Thanks,

0 Eilon Eyal74533 over 8 years ago in reply to Eilon Eyal74533

Intellectual 390 points

Hi Bin,

any update?

Thanks

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

If you have control on the host side to not sending modulo of the max packet, sure this will prevent ZLP issue, but the patch #6.4 in the link below already fixes the TX ZLP handling in MUSB drivers, you don't have to change the host driver/application, since you said you have already applied all the patches #6.1~#6.5.

http://processors.wiki.ti.com/index.php/Sitara_Linux_MUSB_Issues#AMSDK_06.00.00.00

How long does it take to trigger the issue? I am thinking if it is more efficient to debug it if you can ship me the setup then I can debug it locally?

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Hi Bin,

I am looking again on how we applied the 6 patch you provided and I see something strange.

in the 0001-usb-musb-cppi41-transmit-ZLP-using-PIO.patch the first change is :

@@ -627,7 +627,7 @@ static unsigned cppi41_next_tx_segment(struct cppi41_channel *tx_ch)
* then send the zero length packet.
*/
if (!length || (tx_ch->transfer_mode && length % pkt_size == 0))
- num_pds++;
+ tx_ch->zlp_queued = 1;

pkt_size = length;

I can see that in our code the change was done (we have tx_ch->zlp_queued = 1;) But the strange thing is actually outside the patch scope. the line "pkt_size = length;" appears just after the IF statement in your code, but in our code it appears BEFORE the IF statement.

pkt_size = length;
/*
* If length of transmit buffer is 0 or a multiple of the endpoint size,
* then send the zero length packet.
*/
if (!length || (tx_ch->transfer_mode && length % pkt_size == 0))
tx_ch->zlp_queued = 1;

I looked in our clearcase source control to see what was the baseline and it appears that in our code the line "pkt_size = length;" was always before the IF statement

is it possible to have your entire drivers/musb (based on AMSDK 06.00.00.00) after you applied the 6 patch. I would like to do manual diff.

Thanks,

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

Thanks for pointing it out. I updated the patch #6.4 on the wiki. Please test it again.

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Hi Bin

I looked at the patch you sent but it seems that it was not changed. The current patch still has the wrong lines. Also the old patch and the new patch are similar (both in text diff and MD5sum)

could you please check if there was any issue uploading the new patch to the server

Thanks,

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

I tried to download patch #6.4 again, but I got the newer version, not the first one.
I attached the patch below in case you still have issue to download it.

0001-usb-musb-cppi41-transmit-ZLP-using-PIO.patch.gz

0 Bin Liu over 8 years ago in reply to Bin Liu

TI__Guru*** 125156 points

Eilon,

Please apply the following patch as while.

diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 3a7acf7..0b17bf5 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -1974,7 +1974,7 @@ static int musb_schedule(
        best_diff = 4096;
        best_end = -1;

-       for (epnum = 1, hw_ep = musb->endpoints + 1;
+       for (epnum = is_in ? 1 : 6, hw_ep = musb->endpoints + epnum;
                        epnum < musb->nr_endpoints;
                        epnum++, hw_ep++) {
                int     diff;

0 Bin Liu over 8 years ago in reply to Bin Liu

TI__Guru*** 125156 points

Eilon,

Can you please provide the descriptors of the AM335x USB0 gadget (2ECM+1ACM)? You can connect the AM335x USB0 port to a Linux PC and capture the output of command 'lsusb -v -d <vid:pid>' on the PC.

Can you also please provide the patch which create the USB0 composite gadget? I don't think the kernel has the composite gadget driver which does 2ECM+1ACM. I have to check the driver to see if the endpoint assignment has to be changed on the gadget side.

Please also provide the descriptors of the modem on the host port. I will have to check the endpoint assignment change as in the patch above is sufficient.

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

Hi Bin,

first unfortunately the patch you sent is not working (Actually I think you already sent it a few weeks ago)

1 clarification we have 3 ECM + 1 ACM . out of those 3 ECM, 2 are bridged to the modem and 1 is terminated on the Sitara board (used for Qcom-Sitara control) the ACM is also bridged to the modem. our issue happens only on the interfaces which are bridged to the modem (2 ECM + 1 ACM).

Attached is the lsub as you asked,

Thanks,

lsusb.txt

yalone@ayalone-laptop:~$ sudo lsusb -v -d 258d:2000

Bus 001 Device 002: ID 258d:2000  
Device Descriptor:
  bLength                18
  bDescriptorType         1
  bcdUSB               2.00
  bDeviceClass            2 Communications
  bDeviceSubClass         0 
  bDeviceProtocol         0 
  bMaxPacketSize0        64
  idVendor           0x258d 
  idProduct          0x2000 
  bcdDevice            3.16
  iManufacturer           1 MSIL
  iProduct                2 Eilon
  iSerial                11 d79901081600
  bNumConfigurations      1
OTG Descriptor:
  bLength                 3
  bDescriptorType         9
  bmAttributes         0x03
    SRP (Session Request Protocol)
    HNP (Host Negotiation Protocol)
  Configuration Descriptor:
    bLength                 9
    bDescriptorType         2
    wTotalLength          291
    bNumInterfaces          8
    bConfigurationValue     1
    iConfiguration          0 
    bmAttributes         0xe0
      Self Powered
      Remote Wakeup
    MaxPower                2mA
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        0
      bAlternateSetting       0
      bNumEndpoints           1
      bInterfaceClass         2 Communications
      bInterfaceSubClass      6 Ethernet Networking
      bInterfaceProtocol      0 
      iInterface              3 CDC Ethernet Control Model (ECM)
      CDC Header:
        bcdCDC               1.10
      CDC Union:
        bMasterInterface        0
        bSlaveInterface         1 
      CDC Ethernet:
        iMacAddress                      5 0016080299D7
        bmEthernetStatistics    0x00000000
        wMaxSegmentSize               4542
        wNumberMCFilters            0x0000
        bNumberPowerFilters              0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x82  EP 2 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0010  1x 16 bytes
        bInterval               9
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        1
      bAlternateSetting       0
      bNumEndpoints           0
      bInterfaceClass        10 CDC Data
      bInterfaceSubClass      0 Unused
      bInterfaceProtocol      0 
      iInterface              0 
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        1
      bAlternateSetting       1
      bNumEndpoints           2
      bInterfaceClass        10 CDC Data
      bInterfaceSubClass      0 Unused
      bInterfaceProtocol      0 
      iInterface              4 CDC Ethernet Data
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x81  EP 1 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x01  EP 1 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        2
      bAlternateSetting       0
      bNumEndpoints           1
      bInterfaceClass         2 Communications
      bInterfaceSubClass      6 Ethernet Networking
      bInterfaceProtocol      0 
      iInterface              0 
      CDC Header:
        bcdCDC               1.10
      CDC Union:
        bMasterInterface        2
        bSlaveInterface         3 
      CDC Ethernet:
        iMacAddress                      6 0016080299D8
        bmEthernetStatistics    0x00000000
        wMaxSegmentSize               4542
        wNumberMCFilters            0x0000
        bNumberPowerFilters              0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x84  EP 4 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0010  1x 16 bytes
        bInterval               9
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        3
      bAlternateSetting       0
      bNumEndpoints           0
      bInterfaceClass        10 CDC Data
      bInterfaceSubClass      0 Unused
      bInterfaceProtocol      0 
      iInterface              0 
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        3
      bAlternateSetting       1
      bNumEndpoints           2
      bInterfaceClass        10 CDC Data
      bInterfaceSubClass      0 Unused
      bInterfaceProtocol      0 
      iInterface              0 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x83  EP 3 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x02  EP 2 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        4
      bAlternateSetting       0
      bNumEndpoints           1
      bInterfaceClass         2 Communications
      bInterfaceSubClass      6 Ethernet Networking
      bInterfaceProtocol      0 
      iInterface              0 
      CDC Header:
        bcdCDC               1.10
      CDC Union:
        bMasterInterface        4
        bSlaveInterface         5 
      CDC Ethernet:
        iMacAddress                      7 EA2236742513
        bmEthernetStatistics    0x00000000
        wMaxSegmentSize               4542
        wNumberMCFilters            0x0000
        bNumberPowerFilters              0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x86  EP 6 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0010  1x 16 bytes
        bInterval               9
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        5
      bAlternateSetting       0
      bNumEndpoints           0
      bInterfaceClass        10 CDC Data
      bInterfaceSubClass      0 Unused
      bInterfaceProtocol      0 
      iInterface              0 
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        5
      bAlternateSetting       1
      bNumEndpoints           2
      bInterfaceClass        10 CDC Data
      bInterfaceSubClass      0 Unused
      bInterfaceProtocol      0 
      iInterface              0 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x85  EP 5 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x03  EP 3 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
    Interface Association:
      bLength                 8
      bDescriptorType        11
      bFirstInterface         6
      bInterfaceCount         2
      bFunctionClass          2 Communications
      bFunctionSubClass       2 Abstract (modem)
      bFunctionProtocol       1 AT-commands (v.25ter)
      iFunction              10 CDC Serial
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        6
      bAlternateSetting       0
      bNumEndpoints           1
      bInterfaceClass         2 Communications
      bInterfaceSubClass      2 Abstract (modem)
      bInterfaceProtocol      1 AT-commands (v.25ter)
      iInterface              8 CDC Abstract Control Model (ACM)
      CDC Header:
        bcdCDC               1.10
      CDC Call Management:
        bmCapabilities       0x00
        bDataInterface          7
      CDC ACM:
        bmCapabilities       0x02
          line coding and serial state
      CDC Union:
        bMasterInterface        6
        bSlaveInterface         7 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x88  EP 8 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x000a  1x 10 bytes
        bInterval               9
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        7
      bAlternateSetting       0
      bNumEndpoints           2
      bInterfaceClass        10 CDC Data
      bInterfaceSubClass      0 Unused
      bInterfaceProtocol      0 
      iInterface              9 CDC ACM Data
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x87  EP 7 IN
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x04  EP 4 OUT
        bmAttributes            2
          Transfer Type            Bulk
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0200  1x 512 bytes
        bInterval               0
Device Qualifier (for other device speed):
  bLength                10
  bDescriptorType         6
  bcdUSB               2.00
  bDeviceClass            2 Communications
  bDeviceSubClass         0 
  bDeviceProtocol         0 
  bMaxPacketSize0        64
  bNumConfigurations      1
Device Status:     0x0001
  Self Powered
ayalone@ayalone-laptop:~$

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

Please apply the following patch and test it again. It changes the ep assignment on the gadget side.

diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index a9f58da..2d2d29f 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -175,6 +175,9 @@ ep_matches (
        desc->bEndpointAddress &= USB_DIR_IN;
        if (isdigit (ep->name [2])) {
                u8      num = simple_strtoul (&ep->name [2], NULL, 10);
+               /* ep1-10 for IN, ep11-15 for OUT */
+               if (!(desc->bEndpointAddress & USB_DIR_IN) && num < 11)
+                       return 0;
                desc->bEndpointAddress |= num;
 #ifdef MANY_ENDPOINTS
        } else if (desc->bEndpointAddress & USB_DIR_IN) {
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 075aa5f..b745d66 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -1124,15 +1124,18 @@ static struct musb_fifo_cfg mode_4_cfg[] = {
 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
-{ .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
-{ .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
-{ .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
-{ .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
-{ .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
-{ .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
-{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
-{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
-{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
+{ .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 512, },
+{ .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 512, },
+{ .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 512, },
+{ .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 512, },
+{ .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 512, },
+{ .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 512, },
+{ .hw_ep_num = 13, .style = FIFO_TX,   .maxpacket = 512, },
+{ .hw_ep_num = 13, .style = FIFO_RX,   .maxpacket = 512, },
+{ .hw_ep_num = 14, .style = FIFO_TX,   .maxpacket = 512, },
+{ .hw_ep_num = 14, .style = FIFO_RX,   .maxpacket = 512, },
+{ .hw_ep_num = 15, .style = FIFO_TX,   .maxpacket = 512, },
+{ .hw_ep_num = 15, .style = FIFO_RX,   .maxpacket = 512, },
 };

0 Eilon Eyal74533 over 8 years ago in reply to Bin Liu

Intellectual 390 points

4274.usb.zipHi Bin,

I tested the patch you sent but unfortunately it does not solve the issue.

as you requested I am sending you all the code under drivers/usb were we made our changes .

our changes touched f_ecm.c, cdc2.c and u_ether.c , you will also see all the patches we applied from TI

hope this helps

Thanks

0 Bin Liu over 8 years ago in reply to Eilon Eyal74533

TI__Guru*** 125156 points

Eilon,

I reviewed the code but don't have any comment at the moment yet.

You have mentioned that during your debug, you found adding printk() in the driver makes the issue disappear, do you still remember where in the driver the printk() has been added? Please provide the patch if possible.

BTY, I use Lecroy USB protocol analyzer for USB debugging.