We are using Linux-3.2.0-PSP04.06.00.11. for Sitara AM335x (SDK-06.00.00.00)
we have issues with the DVFS and CPU IDLE : generally there is stability issues after adding some improvements to the existing mechanisms
DVFS
We’re using On Demand governor , we added an additional Low Power Opp ( CPU PLL Freq 50 MHz ) , in addition we added DFS mechanism for Core PLL ( 200/100 MHz )
When low power Opp enabled we see some issues
CPU IDLE :
1.We defined 4 IDLE C-states
/* emif_context_save */
enter_ram_self_refresh1:
/* Weak pull down for DQ, DM ddr_data0_ioctrl 0x3FF00003 */
ldr r1, virt_ddr_io_pull1 @ 1440h ddr_data0_ioctrl = 0x3FF00003
ldr r2, susp_io_pull_data
str r2, [r1]
ldr r1, virt_ddr_io_pull2 @1444h ddr_data1_ioctrl = 0x3FF00003
ldr r2, susp_io_pull_data
str r2, [r1]
/* Weak pull down for macro CMD0 */
ldr r1, virt_ddr_cmd0_ioctrl @ 1404h ddr_cmd0_ioctrl = 0xFFE0018B
ldr r2, susp_io_pull_cmd1
str r2, [r1]
/* Weak pull down for macro CMD1 */
ldr r1, virt_ddr_cmd1_ioctrl @1408h ddr_cmd1_ioctrl = 0xFFE0018B
ldr r2, susp_io_pull_cmd1
str r2, [r1]
/*
* Weak pull down for macro CMD2
* exception: keep DDR_RESET pullup
*/
ldr r1, virt_ddr_cmd2_ioctrl @ 140Ch ddr_cmd2_ioctrl = 0xFFA0098B
ldr r2, susp_io_pull_cmd2
str r2, [r1]
/* Disable EMIF at this point */
disable_emif 2, virt_emif_clkctrl @ ldr r1, \emif_addr ;; ldr r2, [r1] ; bic r2, r2, #(3 << 0) ; str r2, [r1]
@ CMD0_REG_PHY_DLL_LOCK_DIFF_0 =& ~0x3;clear 0,1 bis
/* Hold CKE low */
ldr r1, virt_ddr_cke_ctrl @ 131Ch ddr_cke_ctrl = 0
mov r2, #0
str r2, [r1]
/* DDR3 reset override and mDDR mode selection */
ldr r0, virt_ddr_io_ctrl @E04h ddr_io_ctrl = 0x90000000
mov r1, #(0x9 << 28)
str r1, [r0]
/* Disable VTP */
ldr r1, virt_ddr_vtp_ctrl @ E0Ch vtp_ctrl = 1
ldr r2, susp_vtp_ctrl_val
str r2, [r1]
/* Enable SRAM LDO ret mode */
ldr r0, virt_sram_ldo_addr @ 1Ch PRM_LDO_SRAM_MPU_CTRL Register =| 1
ldr r1, [r0]
orr r1, #1
str r1, [r0]
pll_bypass mpu, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
dsb
dmb
isb
wfi
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
/* Relock the PLLs */
pll_lock mpu_abt, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
/* Disable SRAM LDO ret mode */
ldr r0, virt_sram_ldo_addr @ 1Ch PRM_LDO_SRAM_MPU_CTRL Register =& ~1
ldr r1, [r0]
bic r1, #1
str r1, [r0]
/* Enable EMIF */
ldr r1, virt_emif_clkctrl @ @ 1Ch PRM_LDO_SRAM_MPU_CTRL Register = 2
mov r2, #0x2
str r2, [r1]
wait_emif_enable:
ldr r3, [r1]
cmp r2, r3
bne wait_emif_enable
/* DDR3 reset override and mDDR mode clear */
ldr r0, virt_ddr_io_ctrl
/* LPDDR1 io ctrl value write */
lpddr1_io_ctrl_abt: @E04h ddr_io_ctrl = 0x10000000
mov r1, #(0x1 << 28)
str r1, [r0]
/* Enable VTP */
config_vtp_abt:
ldr r0, virt_ddr_vtp_ctrl @ E0Ch vtp_ctrl
ldr r1, [r0]
mov r2, #0x0 @ clear the register
str r2, [r0]
mov r2, #0x6 @ write the filter value
str r2, [r0]
ldr r1, [r0]
ldr r2, vtp_enable @ set the enable bit @ set the enable bit VTP_CTRL_ENABLE (0x1 << 6)
orr r2, r2, r1
str r2, [r0]
ldr r1, [r0] @ toggle the CLRZ bit
bic r1, #1
str r1, [r0]
ldr r1, [r0]
orr r1, #1
str r1, [r0]
poll_vtp_ready_abt:
ldr r1, [r0] @ poll for VTP ready
tst r1, #(1 << 5)
beq poll_vtp_ready_abt
/* Restore the pull for DQ, DM */
ldr r1, virt_ddr_io_pull1 @ 1440h ddr_data0_ioctrl = 0x18B
ldr r2, resume_io_pull_data
str r2, [r1]
ldr r1, virt_ddr_io_pull2 @1444h ddr_data1_ioctrl = 0x18B
ldr r2, resume_io_pull_data
str r2, [r1]
/* Disable the pull for CMD2 */
ldr r1, virt_ddr_cmd2_ioctrl @ 140Ch ddr_cmd2_ioctrl = 0x18B
ldr r2, resume_io_pull_cmd
str r2, [r1]
/* Disable the pull for CMD1 */
ldr r1, virt_ddr_cmd1_ioctrl @1408h ddr_cmd1_ioctrl = 0x18B
ldr r2, resume_io_pull_cmd
str r2, [r1]
/* Disable the pull for CMD0 */
ldr r1, virt_ddr_cmd0_ioctrl @ 1404h ddr_cmd0_ioctrl = 0x18B
ldr r2, resume_io_pull_cmd
str r2, [r1]
/* Restore EMIF control of CKE */
ldr r1, virt_ddr_cke_ctrl @ 131Ch ddr_cke_ctrl = 1
mov r2, #1
str r2, [r1]
emif_self_refresh_dis:
disable_emif_self_refresh emif_addr_virt @ 38h PWR_MGMT_CTRL Register clear bit (0x7 << 8)
@ and write the same value to PWR_MGMT_CTRL_SHDW Register (offset = 3Ch)
/*
* A write to SDRAM CONFIG register triggers
* an init sequence and hence it must be done
* at the end
*/
ldr r0, emif_addr_virt
add r0, r0, #EMIF4_0_SDRAM_CONFIG @ SDRAM_CONFIG Register (offset = 8h) restore register from .macro emif_context_save
ldr r4, emif_sdcfg_val
str r4, [r0]
mov r0, #0x2000
wait_loop4:
subs r0, r0, #1
bne wait_loop4
mov r0, #7
ldmfd sp!, {r4 - r11, pc} @ restore regs and return
