Use of ecap0 ,ecap1 interface for pulse input on AM335x.

Uday Rajeshirke.

Other Parts Discussed in Thread: TLV320AIC3106

Has any body worked on using the ECAP API to develop a pulse input count functionality.

I have to used GPIO pin and used rising edge interrupts for counting pulse. But these have limitation. I need to count a *** of 20 to 20kHz .

AM335x PWM driver doesn't support capture input functionality. but found a ecap_api.c here

brief ECAP APIs.
*
* This file contains the device abstraction layer APIs for ECAP
*/

and a good APIS which can work for you to get functionality from ecap module on AM335x theoritically. Btu the issue is how to provide the base address to these API's.

Need help on this.

Thanks & Regards,

Uday Rajeshirke.

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Is your question Android-related? Android is supported on a dedicated forum: https://e2e.ti.com/support/embedded/android/f/509

0 Uday Rajeshirke. over 8 years ago in reply to Biser Gatchev-XID

Intellectual 620 points

Hi biser,
My question is not about android related.
I am using TI SDK 7.00.00.00 with our custom board having am335x . I need help on writing driver for ecap interface to count the pulses throufh the isr.
I have gone through this post.
e2e.ti.com/.../1056108
Understood what needs to be done . But need some help on how can I hook in to driver to add this functionality.
Thanks & Regards,
Uday Rajehsirke.

0 Biser Gatchev-XID over 8 years ago in reply to Uday Rajeshirke.

TI__Guru**** 393215 points

OK, I notified the Linux team.

0 Uday Rajeshirke. over 8 years ago in reply to Biser Gatchev-XID

Intellectual 620 points

Hi,
waiting for reply.

Thanks & Regards,

0 Yordan Kovachev over 8 years ago in reply to Uday Rajeshirke.

TI__Guru**** 161600 points

Hi Uday,

Is this issue still pending?

First of all you should configure your kernel appropriately, so that it initializes the ecap: clocks, pins, etc... You should create appropriate dts nodes & add the ecap & PWMSS in the kernel configuration (menucaonfig or through the defconfig file directly). Once you've done that your kernel should map the ecap_pwmss to /proc/interrupts, /proc/iomem, etc ... And the module will be accessible from user space.
Working with those fs entries narrows down to using files in your userspce driver.

As I see the ecap.c source you refer to is a user space driver that sets different functionalities of the ecap module. You need to create the appropriate header files: hw_pwmss.h, ecap.h, hw_types.h, hw_ecap.h which hold the definitions of the ECAP, PWMSS, PRCM and ohter used registers ( i couldn't find them in the link you provided, so I assume you'll have to create them yourself); you should define the base addresses from the device TRM.
You should also define the HWREG() & HWREGH() macros for reading/writing to the registers, you can refer to the implementation of devmem2 for reference: free-electrons.com/.../devmem2.c (focus on remapping the base address to the virtual kernel address space).

Then you can create a main() function that calls the apis from ecap.c to do the needed ecap module settings and implement the functionality described in the e2e post you refer. You should cross compile your user space driver and copy the binary to the filesystem on your board.

Hope this helps.
Best Regards,
Yordan

0 Uday Rajeshirke. over 8 years ago in reply to Yordan Kovachev

Intellectual 620 points

Hi Yordan,
Thanks for reply.
I have configured a kernel for ecap driver compilation. I have modified a driver to enable ecap feature. Sysfs interface also done to enable ecap- capture mode. .
But we are facing following problem.
1) IRQ as per technical reference manual for the ECAP- CAP4 is 31 , 47 for ECAP0 ,ECAP1 interface respectively. But when we requesting IRS with this number it is not working a all. Means When we enable the ecap -capture mode it is getting enable but interrupts are not getting genereted when pulse input is provided.
If we request IRS 47 ,63 interrupt is getting generated but it doesnt get stop even if pulse input is stopped. interrupt keeps on happening . We are counting the pulses in interrupt and doing nothing. After some time kernel gets panic and board hangs.

@ Biser need your help in configuring the correct IRQ , disabling the interrupt sequence.
Need urgent help on this. As it is pending for a long time.

Thanking you in anticipation.

Uday R.

0 Yordan Kovachev over 8 years ago in reply to Uday Rajeshirke.

TI__Guru**** 161600 points

Hi Uday,

You should aim for IRQs 31 & 47, which correspond to ECAP0 & ECAP1. Not sure why IRQ63 is generated when using ECAP0 & ECAP1, as it is dedicated to GPIOINT3B (GPIO 3). Can you share your DTS file? I need the pinmux settings & modules configurations?

In order to configure the correct IRQ, you need to ensure that INTC_ILR_31[bit0] = 0x0 & INTC_ILR_47[bit0]=0x0, but this should be the default configuration. However, could you please check the settings of those two registers? Also can you look into the values of ECEINT, ECFLG, ECCLR & ECFRC to ensure that interrupts are enabled on IP level?

Best Regards,
Yordan

0 Uday Rajeshirke. over 8 years ago in reply to Yordan Kovachev

Intellectual 620 points

Hi Yordan,
Following are my device tree entry details related to ecap and the values I can read through sysfs. I have added these functionality for sysfs to return the register values.
Please let me know if you want complete dtsi file.

evice tree entries in dtsi:
epwmss0: epwmss@48300000 {
status = "okay";
ecap0: ecap@48300100 {
compatible = "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
interrupts = <31>;
interrupt-names = "ecap0";
ti,hwmods = "ecap0";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ecap0_pins_default>;
pinctrl-1 = <&ecap0_pins_sleep>;
};
};

epwmss1: epwmss@48302000 {
status = "okay";
ecap1: ecap@48302100 {
compatible = "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
interrupts = <47>;
interrupt-names = "ecap1";
ti,hwmods = "ecap1";
status = "okay";
pinctrl-names = "default", "sleep";

pinctrl-0 = <&ecap1_pins_default>;
pinctrl-1 = <&ecap1_pins_sleep>;
};
};

Console logs:
Configuring through sysfs

root@am335x-evm:~# echo 0 > /sys/class/pwm/pwmchip0/export
root@am335x-evm:~# echo 1 > /sys/class/pwm/pwmchip0/pwm0/enable
[ 26.145684] .....1
[ 26.147855] .....ECAP_ECCLR = 1
[ 26.151148] .....ECCTL2 = 6
[ 26.154073] .....ECAP_ECEINT = 0
root@am335x-evm:~# echo 1 > /sys/class/pwm/pwmchip0/pwm0/period
[ 30.445467] .....2
[ 30.447622] .....ECCTL2 = 86
[ 30.450643] .....ECCTL1 = 155
[ 30.453752] .....prescaler = 0 is set
[ 30.457375] .....ECAP_ECEINT = 10
[ 30.460859] .....ECCTL2 = 96
[ 30.463879] .....ECAP_ECCLR = 0
root@am335x-evm:~# echo 0 > /sys/class/pwm/pwmchip0/pwm0/enable
[ 37.435364] .....nothing

Pulse signal verification:
When no pulse input is fed,
root@am335x-evm:~# echo inversed > /sys/class/pwm/pwmchip0/pwm0/polarity
[ 51.375673] .....3
[ 51.377796] .....ECAP_ECFLG = 2
[ 51.381090] .....cap1 = 0
[ 51.383832] .....cap2 = 0
[ 51.386621] .....cap3 = 0
[ 51.389368] .....cap4 = 0

When pulse input is fed
root@am335x-evm:~# echo inversed > /sys/class/pwm/pwmchip0/pwm0/polarity
[ 56.045556] .....3
[ 56.047683] .....ECAP_ECFLG = 1f
[ 56.051071] .....cap1 = 0
[ 56.053816] .....cap2 = b747
[ 56.056873] .....cap3 = 5343
[ 56.059892] .....cap4 = ef1e
root@am335x-evm:~# echo inversed > /sys/class/pwm/pwmchip0/pwm0/polarity
[ 56.045556] .....3
[ 56.047683] .....ECAP_ECFLG = 1f
[ 56.051071] .....cap1 = 0
[ 56.053816] .....cap2 = b747
[ 56.056873] .....cap3 = 5343
[ 56.059892] .....cap4 = ef1e
root@am335x-evm:~# echo inversed > /sys/class/pwm/pwmchip0/pwm0/polarity
[ 57.485409] .....3
[ 57.487529] .....ECAP_ECFLG = 1f
[ 57.490914] .....cap1 = 8af1
[ 57.493935] .....cap2 = b747
[ 57.496985] .....cap3 = 5343
[ 57.500007] .....cap4 = ef1e

Thanks & Regards,
Uday Rajeshirke.

0 Yordan Kovachev over 8 years ago in reply to Uday Rajeshirke.

TI__Guru**** 161600 points

Hi,

I see that ECAP_ECEINT = 10, which shows that interrupt event4 is enabled. From Table 6-2. Timer and eCAP Event Capture you can see that this is UART3 -> UART3INT.

Can you verify that you don't use uart3, this may be the reason you keep getting interrupts on the UART3INT pin even though you've stopped the input pulses.
Can you try adding interrupt-parent = <&used_irq_parent> to your ecap dts nodes, and see if the behavior of your setup will change?
Also please attach the full DTS & DTSI files you use.

Best Regards,
Yordan

0 Uday Rajeshirke. over 8 years ago in reply to Yordan Kovachev

Intellectual 620 points

Hi ,

We are using a uart3. Following is the dtsi file .

/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/

/ {
   model = "AM335x-EVM";
   compatible = "ti,am335x-bone", "ti,am33xx";

   cpus {
       cpu@0 {
           //cpu0-supply = <&dcdc2_reg>;
       };
   };

   memory {
       device_type = "memory";
       reg = <0x80000000 0x10000000>; /* 256 MB */
   };

   am33xx_pinmux: pinmux@44e10800 {
       pinctrl-names = "default";
       pinctrl-0 = <&clkout1_pin &keys_default>;

        /* Configuring GPIOs for pullup during startup of board */
        keys_default: keys_default {
       pinctrl-single,pins = <
               0x114 (PIN_INPUT_PULLUP | MUX_MODE7)   /* DIG_MPU_IP_2 */
                0x118 (PIN_INPUT_PULLUP | MUX_MODE7)   /* DIG_MPU_IP_1 */
                0x2C (PIN_INPUT_PULLUP | MUX_MODE7)        /*MPU_IGN_IP*/
                0x144 (PIN_INPUT_PULLUP | MUX_MODE7)   /* MPU_KEY_IN_IP */
                0x124 (PIN_INPUT_PULLUP | MUX_MODE7)    /*MPU_PANIC_IP*/
                0x28 (PIN_INPUT_PULLUP | MUX_MODE7)    /*MPU_ACC_IP*/
                0x198 (PIN_INPUT_PULLUP | MUX_MODE7)    /*IO_EXP2_INT*/
                0x1A8 (PIN_INPUT_PULLUP | MUX_MODE7)    /*IO_EXP1_INT*/
                0x24 (PIN_INPUT_PULLUP | MUX_MODE7)    /*ACC_INT1*/
                0x58 (PIN_INPUT_PULLUP | MUX_MODE7)    /*ACC_INT2*/
                0x20 (PIN_INPUT_PULLUP | MUX_MODE7)    /*CAN0_INH*/
                0x80 (PIN_INPUT_PULLUP | MUX_MODE7)    /*TEMP_ALERT*/
                0x38 (PIN_INPUT_PULLUP | MUX_MODE7)    /*GSM_STATUS*/
                0x3C (PIN_INPUT_PULLUP | MUX_MODE7)    /*BATT_CHARGE*/
                0x30 (PIN_INPUT_PULLUP | MUX_MODE7)    /*BATT_FAULT*/
               0xc0 (PIN_OUTPUT | MUX_MODE7 )            /* (U1) lcd_data8.lcd_data8 */
               0x194 (PIN_OUTPUT | MUX_MODE7 )        /* (B13) MPU_BAT_MON_EN */
               0x200 ( PIN_INPUT | MUX_MODE7 )        /* (C5) EXT_WAKEUP.EXT_WAKEUP */
               // 0x164 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
               // 0x160 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (C15) spi0_cs1.eCAP1_in_PWM1_out */
               0xE4 (PIN_INPUT_PULLUP | MUX_MODE7)      /* LCD_HSYNC.gpio2_23, INPUT | MODE7 SIM DETECT*/
               0x1b4 (PIN_INPUT_PULLUP | MUX_MODE7)   /* MPU_AUD_ON_OFF_IP */
                >;
       };

       i2c0_pins: pinmux_i2c0_pins {
           pinctrl-single,pins = <
               0x188 (PIN_INPUT_PULLUP | MUX_MODE0)   /* i2c0_sda.i2c0_sda */
               0x18c (PIN_INPUT_PULLUP | MUX_MODE0)   /* i2c0_scl.i2c0_scl */
           >;
       };

       i2c1_pins: pinmux_i2c1_pins {
           pinctrl-single,pins = <
               0x158 (PIN_INPUT_PULLUP | MUX_MODE2)   /* i2c1_sda.i2c1_sda */
               0x15c (PIN_INPUT_PULLUP | MUX_MODE2)   /* i2c1_scl.i2c1_scl */
           >;
       };

       i2c2_pins: pinmux_i2c2_pins {
           pinctrl-single,pins = <
               0x154 (PIN_INPUT_PULLUP | MUX_MODE2)   /* i2c2_sda.i2c2_sda */
               0x150 (PIN_INPUT_PULLUP | MUX_MODE2)   /* i2c2_scl.i2c2_scl */
           >;
       };

       /* UART pins */

       uart0_pins: pinmux_uart0_pins {
           pinctrl-single,pins = <
               0x170 (PIN_INPUT_PULLUP | MUX_MODE0)   /* uart0_rxd.uart0_rxd */
               0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)   /* uart0_txd.uart0_txd */
           >;
       };

       uart1_pins: pinmux_uart1_pins {
           pinctrl-single,pins = <
               0x178 (PIN_INPUT | MUX_MODE0)           /* uart1_ctsn.uart1_ctsn */
               0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0)   /* uart1_rtsn.uart1_rtsn */
               0x180 (PIN_INPUT_PULLUP | MUX_MODE0)   /* uart1_rxd.uart1_rxd */
               0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
           >;
       };

       uart2_pins: pinmux_uart2_pins {
           pinctrl-single,pins = <
               0x12c (PIN_INPUT_PULLUP | MUX_MODE1)   /* uart2_rxd.uart2_rxd */
               0x130 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)   /* uart2_txd.uart2_txd */
           >;
       };

       uart3_pins: pinmux_uart3_pins {
           pinctrl-single,pins = <
               0x134 (PIN_INPUT_PULLUP | MUX_MODE1)   /* mii1_rxd3.uart3_rxd */
               0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)   /* mii1_rxd2.uart3_txd */
           >;
       };

       uart5_pins: pinmux_uart5_pins {
           pinctrl-single,pins = <
               0x148 (PIN_INPUT_PULLUP | MUX_MODE2)   /* uart5_rxd_mux3 */
               0x14c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)   /* uart5_txd_mux3 */
           >;
       };

       dcan0_pins: pinmux_dcan0_pins {
           pinctrl-single,pins = <
               0x11c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* dcan0_tx_mux0, (IDIS | OFF | MODE1 ) */
               0x120 (PIN_INPUT_PULLUP | MUX_MODE1) /* dcan0_rx_mux0, (IEN | PD | MODE1 ) */
           >;
       };

       dcan1_pins: pinmux_dcan1_pins {
           pinctrl-single,pins = <
                0x168 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* dcan1_tx_mux0, (IDIS | OFF | MODE2 ) */
                0x16c (PIN_INPUT_PULLUP | MUX_MODE2) /* dcan1_rx_mux0, (IEN | OFF | MODE2 ) */
           >;
       };

       clkout1_pin: pinmux_clkout1_pin {
           pinctrl-single,pins = <
               0x1b0 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)   /* xdma_event_intr0.clkout1 */
               // 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)   /* xdma_event_intr1.clkout2 */
           >;
       };

       mmc1_pins_default: pinmux_mmc1_pins {
           pinctrl-single,pins = <
               0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0)   /* mmc0_dat3.mmc0_dat3 */
               0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0)   /* mmc0_dat2.mmc0_dat2 */
               0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0)   /* mmc0_dat1.mmc0_dat1 */
               0x0FC (PIN_INPUT_PULLUP | MUX_MODE0)   /* mmc0_dat0.mmc0_dat0 */
               0x100 (PIN_INPUT_PULLUP | MUX_MODE0)   /* mmc0_clk.mmc0_clk */
               0x104 (PIN_INPUT_PULLUP | MUX_MODE0)   /* mmc0_cmd.mmc0_cmd */
           >;
       };

       mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
           pinctrl-single,pins = <
               0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
           >;
       };

       nandflash_pins_default: nandflash_pins_default {
           pinctrl-single,pins = <
               0x0 (PIN_INPUT_PULLUP | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
               0x4 (PIN_INPUT_PULLUP | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
               0x8 (PIN_INPUT_PULLUP | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
               0xc (PIN_INPUT_PULLUP | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
               0x10 (PIN_INPUT_PULLUP | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
               0x14 (PIN_INPUT_PULLUP | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
               0x18 (PIN_INPUT_PULLUP | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
               0x1c (PIN_INPUT_PULLUP | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
               0x70 (PIN_INPUT_PULLUP | MUX_MODE0)   /* gpmc_wait0.gpmc_wait0 */
               0x74 (PIN_INPUT_PULLUP | MUX_MODE0)   /* gpmc_wpn.gpmc_wpn */
               0x7c (PIN_OUTPUT | MUX_MODE0)       /* gpmc_csn0.gpmc_csn0 */
               0x90 (PIN_OUTPUT | MUX_MODE0)       /* gpmc_advn_ale.gpmc_advn_ale */
               0x94 (PIN_OUTPUT | MUX_MODE0)       /* gpmc_oen_ren.gpmc_oen_ren */
               0x98 (PIN_OUTPUT | MUX_MODE0)       /* gpmc_wen.gpmc_wen */
               0x9c (PIN_OUTPUT | MUX_MODE0)       /* gpmc_be0n_cle.gpmc_be0n_cle */
           >;
       };

       nandflash_pins_sleep: nandflash_pins_sleep {
           pinctrl-single,pins = <
               0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
           >;
       };

       /* Abishek : added for ecap Support */
       ecap0_pins_default: ecap0_pins {
           pinctrl-single,pins = <
               0x164 ( PIN_INPUT | MUX_MODE0 ) /* (C18) eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
           >;
       };

       ecap0_pins_sleep: ecap0_pins_sleep {
           pinctrl-single,pins = <
               0x164 ( PIN_INPUT | MUX_MODE7 ) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
           >;
       };

       ecap1_pins_default: ecap1_pins {
           pinctrl-single,pins = <
               0x160 ( PIN_INPUT | MUX_MODE2 ) /* (C15) spi0_cs1.eCAP1_in_PWM1_out */
           >;
       };

       ecap1_pins_sleep: ecap1_pins_sleep {
           pinctrl-single,pins = <
               0x160 ( PIN_INPUT | MUX_MODE7 ) /* (C15) spi0_cs1.eCAP1_in_PWM1_out */
           >;
       };

       mcasp0_pins: mcasp0_pins {
           pinctrl-single,pins = <
               0x60 (PIN_INPUT_PULLDOWN | MUX_MODE6)
               0x64 (PIN_INPUT_PULLDOWN | MUX_MODE6)
               0x68 (PIN_OUTPUT_PULLDOWN | MUX_MODE6)
               0x6C (PIN_INPUT_PULLDOWN | MUX_MODE6)
           >;
       };

       mcasp0_sleep_pins: mcasp0_sleep_pins {
           pinctrl-single,pins = <
               0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
               0x6C (PIN_INPUT_PULLDOWN | MUX_MODE7)
           >;
       };


       /* Harsha : added for Wi-Fi Support */
       /* wl12xx/wl18xx card on mmc2 */
       mmc2_pins: pinmux_mmc2_pins {
           pinctrl-single,pins = <
               0x44 (PIN_INPUT_PULLUP | MUX_MODE3)   /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
               0x48 (PIN_INPUT_PULLUP | MUX_MODE3)   /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
               0x4C (PIN_INPUT_PULLUP | MUX_MODE3)   /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
               0x78 (PIN_INPUT_PULLUP | MUX_MODE3)   /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
               0x88 (PIN_INPUT_PULLUP | MUX_MODE3)   /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
               0x8C (PIN_INPUT_PULLUP | MUX_MODE3)   /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
           >;
       };

       mmc2_pins_sleep: pinmux_mmc2_pins_sleep {
           pinctrl-single,pins = <
               0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.mmc1_clk */
               0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.mmc1_cmd */
               0x4C (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.mmc1_dat0 */
               0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.mmc1_dat1 */
               0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.mmc1_dat2 */
               0x8C (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.mmc1_dat3 */
           >;
       };

       /* wl12xx/wl18xx card enable/irq GPIOs. */
       wlan_pins: pinmux_wlan_pins {
           pinctrl-single,pins = <
               0x10C (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gmii1_crs.gpio3_1 used for wi-fi EN */
                0x110 (PIN_INPUT_PULLUP | MUX_MODE7) /* MII1_RX_ER.gpio3_2 used for wi-fi IRQ */
           >;
       };

       /* wl12xx/wl18xx card enable/irq GPIOs. */
       wlan_pins_sleep: pinmux_wlan_pins_sleep {
           pinctrl-single,pins = <
               0x10C (PIN_OUTPUT_PULLUP | MUX_MODE7)   /*gmii1_crs.gpio3_1 used for wi-fi EN*/
               0x110 (PIN_INPUT_PULLUP | MUX_MODE7)   /* MII1_RX_ER.gpio3_2 used for wi-fi IRQ */
           >;
       };

   };

   ocp {

       musb: usb@47400000 {
           status = "okay";

           control@44e10000 {
               status = "okay";
           };

           usb-phy@47401300 {
               status = "okay";
           };

           usb-phy@47401b00 {
               status = "okay";
           };

           usb@47401000 {
               status = "okay";
               dr_mode = "otg"; /* Harsha added on 4-12-14 for checking host mode */
           };

           usb@47401800 {
               status = "okay";
               dr_mode = "host";
           };

           dma-controller@07402000 {
               status = "okay";
           };

       };

       i2c0: i2c@44e0b000 {
           pinctrl-names = "default";
           pinctrl-0 = <&i2c0_pins>;
           status = "okay";
           clock-frequency = <400000>;
       };

       i2c1: i2c@4802a000 {
           pinctrl-names = "default";
           pinctrl-0 = <&i2c1_pins>;
           status = "okay";
           clock-frequency = <100000>;
            #if 0
            wake-sequence = /bits/ 8 <
            0x02 0x21 0x06 0xEF /* Make pin as out put WL_EN PIN*/
            0x02 0x21 0x02 0x10 /* Enable the WL_EN pin to high */
            >;

            sleep-sequence = /bits/ 2 <
            0x02 0x21 0x06 0xEF /* Make pin as out put WL_EN PIN*/
            0x02 0x21 0x02 0x10 /* Enable the WL_EN pin to high */
            >;
            #endif

           tlv320aic3106: tlv320aic3106@1b {
               compatible = "ti,tlv320aic3106";
               reg = <0x1b>;
                gpio-reset = <&gpio0 8 0>; /* GPIO_1 AUDIO_CODEC_RST */
               status = "okay";
           };

       };

        i2c2: i2c@4819c000 {
           pinctrl-names = "default";
           pinctrl-0 = <&i2c2_pins>;
           status = "okay";
           clock-frequency = <400000>;
       };

        /* UARTS */
       uart0: serial@44e09000 {
           pinctrl-names = "default";
           pinctrl-0 = <&uart0_pins>;

           status = "okay";
       };

       uart1: serial@48022000 {
           pinctrl-names = "default";
           pinctrl-0 = <&uart1_pins>;

           status = "okay";
       };


       uart2: serial@48024000 {
           pinctrl-names = "default";
           pinctrl-0 = <&uart2_pins>;

           status = "okay";
       };

       uart3: serial@481a6000 {
           pinctrl-names = "default";
           pinctrl-0 = <&uart3_pins>;

           status = "okay";
       };

       uart5: serial@481aa000 {
           pinctrl-names = "default";
           pinctrl-0 = <&uart5_pins>;

           status = "okay";
       };

       dcan0: d_can@481cc000 {
           status = "okay";
           pinctrl-names = "default";
           pinctrl-0 = <&dcan0_pins>;
       };

       dcan1: d_can@481d0000 {
           status = "okay";
           pinctrl-names = "default";
           pinctrl-0 = <&dcan1_pins>;
       };

       /* Abishek : added for ecap Support */
       epwmss0: epwmss@48300000 {
       status = "okay";
       ecap0: ecap@48300100 {
           compatible = "ti,am33xx-ecap";
           #pwm-cells = <3>;
           reg = <0x48300100 0x80>;
           interrupts = <31>;
           interrupt-names = "ecap0";
           ti,hwmods = "ecap0";
           status = "okay";
           pinctrl-names = "default", "sleep";
           pinctrl-0 = <&ecap0_pins_default>;
           pinctrl-1 = <&ecap0_pins_sleep>;
           };
       };

       epwmss1: epwmss@48302000 {
       status = "okay";
       ecap1: ecap@48302100 {
           compatible = "ti,am33xx-ecap";
           #pwm-cells = <3>;
           reg = <0x48302100 0x80>;
           interrupts = <47>;
           interrupt-names = "ecap1";
           ti,hwmods = "ecap1";
           status = "okay";
           pinctrl-names = "default", "sleep";

           pinctrl-0 = <&ecap1_pins_default>;
           pinctrl-1 = <&ecap1_pins_sleep>;
           };
       };

       //200000000 - NAND Size
       gpmc: gpmc@50000000 {
           status = "okay";
           pinctrl-names = "default", "sleep";
           pinctrl-0 = <&nandflash_pins_default>;
           pinctrl-1 = <&nandflash_pins_sleep>;
           ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
           nand@0,0 {
               reg = <0 0 0>; /* CS0, offset 0 */
               nand-bus-width = <8>;
               gpmc,device-width = <1>;
               gpmc,sync-clk-ps = <0>;
               gpmc,cs-on-ns = <0>;
               gpmc,cs-rd-off-ns = <44>;
               gpmc,cs-wr-off-ns = <44>;
               gpmc,adv-on-ns = <6>;
               gpmc,adv-rd-off-ns = <34>;
               gpmc,adv-wr-off-ns = <44>;
               gpmc,we-on-ns = <0>;
               gpmc,we-off-ns = <40>;
               gpmc,oe-on-ns = <0>;
               gpmc,oe-off-ns = <54>;
               gpmc,access-ns = <64>;
               gpmc,rd-cycle-ns = <82>;
               gpmc,wr-cycle-ns = <82>;
               gpmc,wait-on-read = "true";
               gpmc,wait-on-write = "true";
               gpmc,bus-turnaround-ns = <0>;
               gpmc,cycle2cycle-delay-ns = <0>;
               gpmc,clk-activation-ns = <0>;
               gpmc,wait-monitoring-ns = <0>;
               gpmc,wr-access-ns = <40>;
               gpmc,wr-data-mux-bus-ns = <0>;
               ti,nand-ecc-opt= "bch8";
               ti,elm-id = <&elm>;
               /* MTD partition table */
                        /* All SPL-* partitions are sized to minimal length
               * which can be independently programmable. For
               * NAND flash this is equal to size of erase-block */
               #address-cells = <1>;
               #size-cells = <1>;
               partition@0 {
                   label = "NAND.SPL";
                   reg = <0x00000000 0x000020000>;
               };
               partition@1 {
                   label = "NAND.SPL.backup1";
                   reg = <0x00020000 0x00020000>;
               };
               partition@2 {
                   label = "NAND.SPL.backup2";
                   reg = <0x00040000 0x00020000>;
               };
               partition@3 {
                   label = "NAND.SPL.backup3";
                   reg = <0x00060000 0x00020000>;
               };
               partition@4 {
                   label = "NAND.u-boot-spl-os";
                   reg = <0x00080000 0x00040000>;
               };
               partition@5 {
                   label = "NAND.u-boot";
                   reg = <0x000C0000 0x00100000>;
               };
               partition@6 {
                   label = "NAND.u-boot-env";
                   reg = <0x001C0000 0x00020000>;
               };
               partition@7 {
                   label = "NAND.u-boot-env.backup1";
                   reg = <0x001E0000 0x00020000>;
               };
               partition@8 {
                   label = "NAND.kernel";
                   reg = <0x00200000 0x00800000>;
               };
               partition@9 {
                   label = "NAND.file-system";
                   reg = <0x00A00000 0x0F600000>;
               };
                partition@10 {
                   label = "NAND.file-system2";
                   reg = <0x10000000 0x30000000>;
               };
           };
       };

        sound {
                compatible = "ti,da830-evm-audio";
                ti,model = "AM335x-EVM";
                ti,audio-codec = <&tlv320aic3106>;
                ti,mcasp-controller = <&mcasp0>;
                ti,codec-clock-rate = <24000000>;
                ti,audio-routing =
                    "Headphone Jack",       "HPLOUT",
                    "Headphone Jack",       "HPROUT";
                    #if 0
                    "LINE1L",               "Line In",
                    "LINE1R",               "Line In";
                    #endif
        };
   };


    wlan_en_reg: fixedregulator@2 {
        compatible = "regulator-fixed";
        regulator-name = "wlan-en-regulator";
         regulator-min-microvolt = <1800000>;
         regulator-max-microvolt = <1800000>;
        /* WLAN_EN GPIO for this board - Bank3, pin1 */
        gpio = <&gpio3 1 0>;

        /* WLAN card specific delay */
        startup-delay-us = <70000>;
       enable-active-high;
    };

#if 0
/* Ref. from file linux3.12/include/linux/wl12xx.h */
/* Reference clock values */
enum {
   WL12XX_REFCLOCK_19   = 0, /* 19.2 MHz */
   WL12XX_REFCLOCK_26   = 1, /* 26 MHz */
   WL12XX_REFCLOCK_38   = 2, /* 38.4 MHz */
   WL12XX_REFCLOCK_52   = 3, /* 52 MHz */
   WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
   WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
};
#endif

   wlcore {
       compatible = "wlcore";
       gpio = <98>; /* Bank3, pin2 GPIO for Wi-Fi_IRQ */

       /*
       * TODO: use edge irqs for suspend/resume.
       * in newer kerenls, we seem to miss interrupts when
       * working with edge irqs, so revert back to level irqs.
       */
       /* platform-quirks = <1>; */

       /* if a 12xx card is there, configure the clock to
           WL12XX_REFCLOCK_38_XTAL */
       board-ref-clock = <4>;
   };

   vmmcsd_fixed: fixedregulator@0 {
       compatible = "regulator-fixed";
       regulator-name = "vmmcsd_fixed";
       regulator-min-microvolt = <3300000>;
       regulator-max-microvolt = <3300000>;
   };
};

&mcasp0 {
       pinctrl-names = "default", "sleep";
       pinctrl-0 = <&mcasp0_pins>;
       pinctrl-1 = <&mcasp0_sleep_pins>;

       status = "okay";

       op-mode = <0>;          /* MCASP_IIS_MODE */
       tdm-slots = <2>;
       /* 16 serializer */
       serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
           1 2 0 0
       >;
       tx-num-evt = <32>;
       rx-num-evt = <32>;
};

&mmc3 {
    /*these are on the crossbar and are outlined in the
    xbar-event-map element */
    dmas = <&edma 12
    &edma 13>;
    dma-names = "tx", "rx";
    status = "okay";
    vmmc-supply = <&wlan_en_reg>;
    bus-width = <4>;
    pinctrl-names = "default";
    pinctrl-0 = < &mmc2_pins &wlan_pins >;
    pinctrl-1 = < &mmc2_pins_sleep &wlan_pins_sleep >;
    ti,non-removable;
    ti,needs-special-hs-handling;
    cap-power-off-card;
    keep-power-in-suspend;
};

&edma {
    ti,edma-xbar-event-map = <1 12
    2 13>;
};

Thanks & Regards,

Uday Rajeshirke.

0 Abishek Sethu over 8 years ago in reply to Yordan Kovachev

Prodigy 45 points

Hi Yordan,

I wish to post the scenario in detail,

1. Is this configuration strategy right for ECAP capture mode?

From Technical Reference, I want to configure for (15.3.3.3) Time Difference (Delta) Operation Rising Edge Trigger. (Followed)

Uday has posted our dtsi file too...

In pwm-tiecap.c,
We have configured required registers in ecap_pwm_config and ecap_pwm_enable functions. When accessing sysfs files, It is getting executed. Following are the logs.

root@am335x-evm:~# echo 0 > /sys/class/pwm/pwmchip0/export
root@am335x-evm:~# echo 1 > /sys/class/pwm/pwmchip0/pwm0/period
root@am335x-evm:~# echo 1 > /sys/class/pwm/pwmchip0/pwm0/enable
[ 39.679994] .....ECCTL1 = 1aa
[ 39.683134] .....ECCTL2 = 96
[ 39.686159] .....ECEINT = 2
[ 39.689182] .....ECFLG = 0
[ 39.692164] .....ECCLR = 0
(Register Values are in Hex format)

These are the final values and i have configured the ECCTL2_TSCTR_FREERUN counter in ecap_pwm_enable function as free run.

2. If the above method is right, In probe function for ecap0,
we are using following methods to get the ISR for ecap0
As reference says to use 31 for ecap0.

code snippet:
irq = platform_get_irq(pdev,31);
irq_num = 31;
if(devm_request_irq(&pdev->dev, irq_num, (irq_handler_t)pulse_handlers,
__IRQF_TIMER | IRQF_TRIGGER_RISING, pulse_input_name, pc ))

I am not able to get ISR called when i feed pulse input in the ecap pin.

Please support to solve the issue.
Thank you in advance .

Best regards,
Abishek.

0 Yordan Kovachev over 8 years ago in reply to Abishek Sethu

TI__Guru**** 161600 points

Hi Abishek,

The ecap sequence seem to be correct.

I am looking at your irq issue, but I'm not sure why you don't get the interrupts... the irq request you use looks correct. Is it possible that you've requested this interrupt for some other module?

Another point I have is:
I see that you set ECEINT = 2, this means that only capture event 1 of the ecap module is enabled as interrupt source. Can you try enabling all capture events (1 through 4) to be interrupt sources, that is write 1 to bits 1 through 4 of ECEINT. Also try enablint the interrupts (bits 5 through 7 of the same registers).

Best Regards,
Yordan

0 Uday Rajeshirke. over 8 years ago in reply to Uday Rajeshirke.

Intellectual 620 points

Hi Yordan,

Did you find any conflicts in device tree related to eCap interrupt?
I tried to give interrupt-parent tag in device tree with this kernel gets panic at boot up only.

Thnaks & Regards,
Uday Rajeshirke.

0 Yordan Kovachev over 8 years ago in reply to Uday Rajeshirke.

TI__Guru**** 161600 points

Hi Uday,

Uday Rajeshirke. said:
Did you find any conflicts in device tree related to eCap interrupt?

I didn't notice conflicts in device tree. This should work. I will try to reproduce this irq problem (adding irq-parent) on my BBB.

Best Regards,
Yordan

0 Uday Rajeshirke. over 8 years ago in reply to Yordan Kovachev

Intellectual 620 points

Hi Yordan,
My problem of continuous interrupt getting even if I removed a pulse is solve.
And IRQ47,IRQ63 working and not 31,47 as per TRM is not working.
We are using a divide by 60 pre-scaler, with this this it works fine till 7Khz pulse input above this we are getting following error contineously.

[ 83.041945] BUG: scheduling while atomic: swapper/0/0x40010000
[ 83.048103] Modules linked in: wlcore_sdio(O) musb_dsps musb_hdrc compat(O) snd_soc_omap snd_pcm_dmaengine snd_soc_evm snd_soc_tlv320aic3x x
[ 83.078697] CPU: 0 PID: 0 Comm: swapper Tainted: G O 3.12.10-ti2013.12.01 #75
[ 83.087122] Backtrace:
[ 83.089725] [<c0017880>] (dump_backtrace+0x0/0x10c) from [<c0017a1c>] (show_stack+0x18/0x1c)
[ 83.098600] r6:c0718000 r5:c076ce20 r4:00000000 r3:00000000
[ 83.104587] [<c0017a04>] (show_stack+0x0/0x1c) from [<c04fb69c>] (dump_stack+0x20/0x28)
[ 83.113018] [<c04fb67c>] (dump_stack+0x0/0x28) from [<c04f9994>] (__schedule_bug+0x4c/0x64)
[ 83.121813] [<c04f9948>] (__schedule_bug+0x0/0x64) from [<c04fe0cc>] (__schedule+0x364/0x3cc)
[ 83.130774] r4:c07233a0 r3:00000000
[ 83.134552] [<c04fdd68>] (__schedule+0x0/0x3cc) from [<c0067948>] (__cond_resched+0x28/0x38)
[ 83.143432] [<c0067920>] (__cond_resched+0x0/0x38) from [<c04fe1d0>] (_cond_resched+0x40/0x48)
[ 83.152494] r4:cd19b210 r3:00010000
[ 83.156283] [<c04fe190>] (_cond_resched+0x0/0x48) from [<c02efe60>] (__pm_runtime_resume+0x6c/0x74)
[ 83.165823] [<c02efdf4>] (__pm_runtime_resume+0x0/0x74) from [<c0246eac>] (pulse_ip1_handler+0x1c/0x8c)
[ 83.175704] r5:0000002f r4:cd1b4bd0
[ 83.179486] [<c0246e90>] (pulse_ip1_handler+0x0/0x8c) from [<c007162c>] (handle_irq_event_percpu+0x54/0x1b8)
[ 83.189818] r5:0000002f r4:cd1b5780
[ 83.193597] [<c00715d8>] (handle_irq_event_percpu+0x0/0x1b8) from [<c00717c0>] (handle_irq_event+0x30/0x40)
[ 83.203870] [<c0071790>] (handle_irq_event+0x0/0x40) from [<c0073b78>] (handle_level_irq+0x88/0xdc)
[ 83.213391] r4:cd005940 r3:00020000
[ 83.217168] [<c0073af0>] (handle_level_irq+0x0/0xdc) from [<c0070f34>] (generic_handle_irq+0x28/0x38)
[ 83.226872] r4:0000002f r3:c0073af0
[ 83.230657] [<c0070f0c>] (generic_handle_irq+0x0/0x38) from [<c0015560>] (handle_IRQ+0x38/0x8c)
[ 83.239802] r4:c07733a0 r3:00000112
[ 83.243574] [<c0015528>] (handle_IRQ+0x0/0x8c) from [<c000879c>] (omap3_intc_handle_irq+0x68/0x7c)
[ 83.252997] r6:c07a1f14 r5:c0719ee8 r4:fa200000 r3:00000080
[ 83.258976] [<c0008734>] (omap3_intc_handle_irq+0x0/0x7c) from [<c04ff4c0>] (__irq_svc+0x40/0x54)
[ 83.268304] Exception stack(0xc0719ee8 to 0xc0719f30)
[ 83.273624] 9ee0: c0719f30 3b9aca00 000209a6 00000013 551b7705 00000013
[ 83.282244] 9f00: c0790860 00000001 00000000 413fc082 c07a1114 c0719f5c 0000001a c0719f30
[ 83.290854] 9f20: c00779a8 c040c2d8 200f0013 ffffffff
[ 83.296154] r7:c0719f1c r6:ffffffff r5:200f0013 r4:c040c2d8
[ 83.302135] [<c040c27c>] (cpuidle_enter_state+0x0/0xf0) from [<c040c410>] (cpuidle_idle_call+0xa4/0x148)
[ 83.312090] r7:c07d2b60 r6:c0726828 r5:00000001 r4:c0790860
[ 83.318065] [<c040c36c>] (cpuidle_idle_call+0x0/0x148) from [<c0015730>] (arch_cpu_idle+0x10/0x4c)
[ 83.327493] r8:00000001 r7:c07a1114 r6:c0720104 r5:00000000 r4:c0718000
r3:00000000
[ 83.335775] [<c0015720>] (arch_cpu_idle+0x0/0x4c) from [<c0070df0>] (cpu_startup_entry+0x58/0xf4)
[ 83.345119] [<c0070d98>] (cpu_startup_entry+0x0/0xf4) from [<c04f6398>] (rest_init+0x64/0x7c)
[ 83.354083] r7:c09e6980 r3:00000000
[ 83.357859] [<c04f6334>] (rest_init+0x0/0x7c) from [<c06c1a48>] (start_kernel+0x2a0/0x2fc)
[ 83.366574] [<c06c17a8>] (start_kernel+0x0/0x2fc) from [<80008070>] (0x80008070)
[ 83.374393] BUG: scheduling while atomic: swapper/0/0x40010000
[ 83.380526] Modules linked in: wlcore_sdio(O) musb_dsps musb_hdrc compat(O) snd_soc_omap snd_pcm_dmaengine snd_soc_evm snd_soc_tlv320aic3x x
[ 83.411035] CPU: 0 PID: 0 Comm: swapper Tainted: G W O 3.12.10-ti2013.12.01 #75
[ 83.419440] Backtrace:
[ 83.422020] [<c0017880>] (dump_backtrace+0x0/0x10c) from [<c0017a1c>] (show_stack+0x18/0x1c)
[ 83.430885] r6:c0718000 r5:c076ce20 r4:00000000 r3:00000000
[ 83.436853] [<c0017a04>] (show_stack+0x0/0x1c) from [<c04fb69c>] (dump_stack+0x20/0x28)
[ 83.445268] [<c04fb67c>] (dump_stack+0x0/0x28) from [<c04f9994>] (__schedule_bug+0x4c/0x64)
[ 83.454046] [<c04f9948>] (__schedule_bug+0x0/0x64) from [<c04fe0cc>] (__schedule+0x364/0x3cc)
[ 83.463007] r4:c07233a0 r3:00000000
[ 83.466785] [<c04fdd68>] (__schedule+0x0/0x3cc) from [<c0067948>] (__cond_resched+0x28/0x38)
[ 83.475660] [<c0067920>] (__cond_resched+0x0/0x38) from [<c04fe1d0>] (_cond_resched+0x40/0x48)
[ 83.484703] r4:cd19b210 r3:00010000
[ 83.488474] [<c04fe190>] (_cond_resched+0x0/0x48) from [<c02efe60>] (__pm_runtime_resume+0x6c/0x74)
[ 83.497994] [<c02efdf4>] (__pm_runtime_resume+0x0/0x74) from [<c0246eac>] (pulse_ip1_handler+0x1c/0x8c)
[ 83.507858] r5:0000002f r4:cd1b4bd0
[ 83.511628] [<c0246e90>] (pulse_ip1_handler+0x0/0x8c) from [<c007162c>] (handle_irq_event_percpu+0x54/0x1b8)
[ 83.521955] r5:0000002f r4:cd1b5780
[ 83.525729] [<c00715d8>] (handle_irq_event_percpu+0x0/0x1b8) from [<c00717c0>] (handle_irq_event+0x30/0x40)
[ 83.535984] [<c0071790>] (handle_irq_event+0x0/0x40) from [<c0073b78>] (handle_level_irq+0x88/0xdc)
[ 83.545489] r4:cd005940 r3:00020000
[ 83.549260] [<c0073af0>] (handle_level_irq+0x0/0xdc) from [<c0070f34>] (generic_handle_irq+0x28/0x38)
[ 83.558944] r4:0000002f r3:c0073af0
[ 83.562711] [<c0070f0c>] (generic_handle_irq+0x0/0x38) from [<c0015560>] (handle_IRQ+0x38/0x8c)
[ 83.571844] r4:c07733a0 r3:00000112
[ 83.575610] [<c0015528>] (handle_IRQ+0x0/0x8c) from [<c000879c>] (omap3_intc_handle_irq+0x68/0x7c)
[ 83.585024] r6:c07a1f14 r5:c0719ee8 r4:fa200000 r3:00000080
[ 83.590989] [<c0008734>] (omap3_intc_handle_irq+0x0/0x7c) from [<c04ff4c0>] (__irq_svc+0x40/0x54)
[ 83.600309] Exception stack(0xc0719ee8 to 0xc0719f30)
[ 83.605619] 9ee0: c0719f30 3b9aca00 000209a6 00000013 551b7705 00000013
[ 83.614210] 9f00: c0790860 00000001 00000000 413fc082 c07a1114 c0719f5c 0000001a c0719f30
[ 83.622801] 9f20: c00779a8 c040c2d8 200f0013 ffffffff
[ 83.628107] r7:c0719f1c r6:ffffffff r5:200f0013 r4:c040c2d8
[ 83.634071] [<c040c27c>] (cpuidle_enter_state+0x0/0xf0) from [<c040c410>] (cpuidle_idle_call+0xa4/0x148)
[ 83.644023] r7:c07d2b60 r6:c0726828 r5:00000001 r4:c0790860
[ 83.649995] [<c040c36c>] (cpuidle_idle_call+0x0/0x148) from [<c0015730>] (arch_cpu_idle+0x10/0x4c)
[ 83.659402] r8:00000001 r7:c07a1114 r6:c0720104 r5:00000000 r4:c0718000
r3:00000000
[ 83.667665] [<c0015720>] (arch_cpu_idle+0x0/0x4c) from [<c0070df0>] (cpu_startup_entry+0x58/0xf4)
[ 83.677001] [<c0070d98>] (cpu_startup_entry+0x0/0xf4) from [<c04f6398>] (rest_init+0x64/0x7c)
[ 83.685971] r7:c09e6980 r3:00000000
[ 83.689740] [<c04f6334>] (rest_init+0x0/0x7c) from [<c06c1a48>] (start_kernel+0x2a0/0x2fc)
[ 83.698432] [<c06c17a8>] (start_kernel+0x0/0x2fc) from [<80008070>] (0x80008070)
[ 83.706300] ------------[ cut here ]------------
[ 83.711181] WARNING: CPU: 0 PID: 0 at kernel/irq/handle.c:146 handle_irq_event_percpu+0x198/0x1b8()
[ 83.720697] irq 47 handler pulse_ip1_handler+0x0/0x8c enabled interrupts
[ 83.727737] Modules linked in: wlcore_sdio(O) musb_dsps musb_hdrc compat(O) snd_soc_omap snd_pcm_dmaengine snd_soc_evm snd_soc_tlv320aic3x x
[ 83.758235] CPU: 0 PID: 0 Comm: swapper Tainted: G W O 3.12.10-ti2013.12.01 #75
[ 83.766636] Backtrace:
[ 83.769212] [<c0017880>] (dump_backtrace+0x0/0x10c) from [<c0017a1c>] (show_stack+0x18/0x1c)
[ 83.778069] r6:c0071770 r5:00000009 r4:c0719e08 r3:00000000
[ 83.784036] [<c0017a04>] (show_stack+0x0/0x1c) from [<c04fb69c>] (dump_stack+0x20/0x28)
[ 83.792450] [<c04fb67c>] (dump_stack+0x0/0x28) from [<c0046d08>] (warn_slowpath_common+0x70/0x90)
[ 83.801776] [<c0046c98>] (warn_slowpath_common+0x0/0x90) from [<c0046dcc>] (warn_slowpath_fmt+0x38/0x40)
[ 83.811729] r8:0000002f r7:00000000 r6:00000000 r5:00000001 r4:cd1b5780
[ 83.818796] [<c0046d94>] (warn_slowpath_fmt+0x0/0x40) from [<c0071770>] (handle_irq_event_percpu+0x198/0x1b8)
[ 83.829206] r3:0000002f r2:c06276c8
[ 83.832973] [<c00715d8>] (handle_irq_event_percpu+0x0/0x1b8) from [<c00717c0>] (handle_irq_event+0x30/0x40)
[ 83.843205] [<c0071790>] (handle_irq_event+0x0/0x40) from [<c0073b78>] (handle_level_irq+0x88/0xdc)
[ 83.852701] r4:cd005940 r3:00020000
[ 83.856469] [<c0073af0>] (handle_level_irq+0x0/0xdc) from [<c0070f34>] (generic_handle_irq+0x28/0x38)
[ 83.866146] r4:0000002f r3:c0073af0
[ 83.869913] [<c0070f0c>] (generic_handle_irq+0x0/0x38) from [<c0015560>] (handle_IRQ+0x38/0x8c)
[ 83.879041] r4:c07733a0 r3:00000112
[ 83.882808] [<c0015528>] (handle_IRQ+0x0/0x8c) from [<c000879c>] (omap3_intc_handle_irq+0x68/0x7c)
[ 83.892213] r6:c07a1f14 r5:c0719ee8 r4:fa200000 r3:00000080
[ 83.898182] [<c0008734>] (omap3_intc_handle_irq+0x0/0x7c) from [<c04ff4c0>] (__irq_svc+0x40/0x54)
[ 83.907501] Exception stack(0xc0719ee8 to 0xc0719f30)
[ 83.912805] 9ee0: c0719f30 3b9aca00 000209a6 00000013 551b7705 00000013
[ 83.921392] 9f00: c0790860 00000001 00000000 413fc082 c07a1114 c0719f5c 0000001a c0719f30
[ 83.929983] 9f20: c00779a8 c040c2d8 200f0013 ffffffff
[ 83.935282] r7:c0719f1c r6:ffffffff r5:200f0013 r4:c040c2d8
[ 83.941249] [<c040c27c>] (cpuidle_enter_state+0x0/0xf0) from [<c040c410>] (cpuidle_idle_call+0xa4/0x148)
[ 83.951195] r7:c07d2b60 r6:c0726828 r5:00000001 r4:c0790860
[ 83.957162] [<c040c36c>] (cpuidle_idle_call+0x0/0x148) from [<c0015730>] (arch_cpu_idle+0x10/0x4c)
[ 83.966569] r8:00000001 r7:c07a1114 r6:c0720104 r5:00000000 r4:c0718000
r3:00000000
[ 83.974825] [<c0015720>] (arch_cpu_idle+0x0/0x4c) from [<c0070df0>] (cpu_startup_entry+0x58/0xf4)
[ 83.984152] [<c0070d98>] (cpu_startup_entry+0x0/0xf4) from [<c04f6398>] (rest_init+0x64/0x7c)
[ 83.993100] r7:c09e6980 r3:00000000
[ 83.996868] [<c04f6334>] (rest_init+0x0/0x7c) from [<c06c1a48>] (start_kernel+0x2a0/0x2fc)
[ 84.005550] [<c06c17a8>] (start_kernel+0x0/0x2fc) from [<80008070>] (0x80008070)
[ 84.013316] ---[ end trace a84661866a719316 ]---

primarily it seems a scheduling error when interrupts are more.
Need your help in resolving the same now.

Thanks & Regards,
Uday Rajeshirke.

0 Yordan Kovachev over 8 years ago in reply to Uday Rajeshirke.

TI__Guru**** 161600 points

Hi Uday,

Sorry for the delayed response.

Have you tried diabling the modules linked in the kernel panic? That is disable wl_sdio, usb_dsps, musb_hdrc & audio drivers.

Also can you share your code for handling the generated interrupts?

I couldn't find anything in the DM or TRM stating that the max frequency that can be fed to ECAP0_IN_PWM0_OUT is 7 kHz.

Best Regards,
Yordan

0 Yordan Kovachev over 8 years ago in reply to Yordan Kovachev

TI__Guru**** 161600 points

Also can you try the maximum possible value of the prescaler, which is 62? It should allow to feed signal with a little higher frequency on your ECAP pin.

Best Regards,
Yordan

Processors

Processors forum

Use of ecap0 ,ecap1 interface for pulse input on AM335x.