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AM335x u-boot add logo (LIDD interface)

Bernie Chen
Expert 2190 points

We adapt the ST7735R LCD (126*168 TFT 16bit 565 mode) 8080 mode, and I have referenced   drivers/lcd Leonerdo supplies in below address and reference am335x TRM chapter 13.3.4 (LIDD controller).

BSP version: sdk6

   

image.h :

#ifndef CONFIG_SPL_BUILD
unsigned int const image1[] __attribute__((aligned(4)))= {
0x4000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u,

..

};

#endif

#define SOC_LCDC_0_REGS                     0x4830E000

#define LCDC_CLKC_ENABLE   (0x6C)

#define LCDC_RASTER_CTRL   (0x28)

#define LCDC_LCD_CTRL   (0x4)

#define LCDC_LIDD_CTRL   (0xC)

#define LCDC_LCDDMA_CTRL   (0x40)

#define LCDC_CLKC_ENABLE_CORE   (0x00000001u)

#define LCDC_CLKC_ENABLE_DMA   (0x00000004u)

#define LCDC_CLKC_ENABLE_LIDD   (0x00000002u)

#define LCDC_RASTER_CTRL_RASTER_EN   (0x00000001u)

#define LCDC_LCD_CTRL_MODESEL_LIDD   (0x0u)

#define LCDC_LCD_CTRL_CLKDIV_SHIFT   (0x00000008u)

#define LCDC_LIDD_CTRL_LIDD_DMA_EN_ACTIVATE   (0x1u)

#define LCDC_LIDD_CTRL_LIDD_DMA_EN_SHIFT   (0x00000008u)

#define LCDC_LCDDMA_CTRL_FRAME_MODE   (0x00000001u)

#define LCDC_LCDDMA_CTRL_BURST_SIZE_SHIFT   (0x00000004u)

#define LCDC_LCDDMA_CTRL_TH_FIFO_READY_SHIFT   (0x00000008u)

#define LCDC_LIDD_CTRL_LIDD_MODE_SEL_SYNC_MPU80   (0x2u)

lidd.c:

                       # include "image.h"

                      int  Lcd_Init (){

                             unsigned int clkDiv;

                           /*  **Clock for DMA,LIDD and for Core(which encompasses
                               ** Raster Active Matrix and Passive Matrix logic) 
                               ** enabled. */

                       HWREG(SOC_LCDC_0_REGS + LCDC_CLKC_ENABLE) =  (LCDC_CLKC_ENABLE_CORE | LCDC_CLKC_ENABLE_DMA  | LCDC_CLKC_ENABLE_LIDD);

                         /* Disable raster */

                       HWREG(SOC_LCDC_0_REGS + LCDC_RASTER_CTRL) &= ~LCDC_RASTER_CTRL_RASTER_EN;

               

                        /* Configure the pclk */

                        clkDiv = 192000000 / 23040000 ;

                       HWREG(SOC_LCDC_0_REGS + LCDC_LCD_CTRL) = LCDC_LCD_CTRL_MODESEL_LIDD; 
                       HWREG(SOC_CLDC_0_REGS + LCDC_LCD_CTRL) |= (clkDiv <<  LCDC_LCD_CTRL_CLKDIV_SHIFT);

                      /* DMA enable in lidd mode */

                     HWREG(SOC_LCDC_0_REGS + LCDC_LIDD_CTRL) = (LCDC_LIDD_CTRL_LIDD_DMA_EN_ACTIVATE << LCDC_LIDD_CTRL_LIDD_DMA_EN_SHIFT);

                      /* Configuring DMA of LCD controller */
                      HWREG(SOC_LCDC_0_REGS + LCDC_LCDDMA_CTRL) = LCDC_LCDDMA_CTRL_FRAME_MODE | (4 <<LCDC_LCDDMA_CTRL_BURST_SIZE_SHIFT ) | (0 << LCDC_LCDDMA_CTRL_TH_FIFO_READY_SHIFT) | 0;
  
                          // Configuring the base ceiling 
                         HWREG(SOC_LCDC_0_REGS + LCDC_LCDDMA_FB0_BASE) = (unsigned int)image1 ;
                         HWREG(baseAddr + LCDC_LCDDMA_FB0_CEILING) = (unsigned int)image1 + sizeof(image1) - 2;

                         HWREG(SOC_LCDC_0_REGS + LCDC_LCDDMA_FB1_BASE) = (unsigned int)image1 ;
                         HWREG(baseAddr + LCDC_LCDDMA_FB0_CEILING) = (unsigned int)image1 + sizeof(image1) - 2;

                         // Enable End of frame0/frame1 interrupt

                         HWREG(SOC_LCDC_0 + LCDC_IRQENABLE_SET) = (RASTER_END_OF_FRAME0_INT | RASTER_END_OF_FRAME1_INT);
                    

                       // RasterModeConfig(SOC_LCDC_0_REGS, RASTER_DISPLAY_MODE_TFT_UNPACKED,
                                                            RASTER_PALETTE_DATA, RASTER_COLOR, RASTER_RIGHT_ALIGNED); 

                       But panel have no picture in screen. I have two question to ask.

              

                       1 These process for initializing LIDD mode above are correct?

                       2 Do I need write something to initial LCD panel?

      Thank you, TI. 

  • 0
    TI__Guru**** 393215 points

    Hi,

    The post you refer and drivers in it are for raster mode displays. Have you got your display working in the kernel?

  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Hi Biser

    Our customer have developed in kernel, so the panel has no issue. and I reference the pseudo code in 13.4.1.3.2

    and LCD_DATA0~LCD_DATA9 have data signal, only VSYNC and PCLK are weird.  VSYNC has no signal, PCLK has singal when in kernel, but u-boot has anything.  Do you have any suggestion for me ? Thank you.

    //EnableClocks
    wr 006C 0000_0007
    //LCD Control Register
    wr 0004 0000_8000          //set clock divisor
    //LIDD Control Register
    wr 000C 0000_000C          //set output bus polarities and lidd_mode_sel
    //LIDD CS0 Register
    wr 0010 0822_1044          //set bus timing parameters for CS0
    //DMA Control Register
    wr 0040 0000_0030          //set DMA parameters like burst size, memory layout
    //DMA FB0 Base Register
    wr 0044 0000_0004          //DMA start byte address
    //DMA FB0 Ceiling Register
    wr 0048 0000_003C          //DMA end byte address
    //LIDD Control Register - enable DMA
    wr 000C 0000_010C          // Flip LIDD DMA enable bit

  • 0
    TI__Guru**** 393215 points

    In your sequence you are enabling the DMA before configuring it. This does not correspond to the TRM sequence.

  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points
    Hi Biser

    I have instead of original by TRM's sequence completely. But VSYNC and PCLK are weird.
    Thank you.
  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    Please see Table 13-4 in the AM335X TRM Rev. L and section 7.10.1 of the AM335X Datasheet Rev. H for the meaning of these signals in LIDD mode.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Dear Biser

    LCD_VSYNC - LIDD graphics: Address bit 0 (A0) or command/data select (C/D)
    LCD_PCLK - LIDD graphic:
    .8080 mode = not read strobe

    Indeed, I don't understand what they are meaning, could you please explain to me for the point of view of software?  In  Particular "read strobe" Thank you. Biser.

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points

    From SW point of view they have no meaning. These are 8080 interface control signals, not H/V sync signals. "Not read strobe" means that the read strobe is active low, but you cannot read data from the LIDD display when you use DMA mode.

  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points
    Dear Biser

    Does active low that means when signal low I can read data from display, and high means when signal high I can't read data from display? Thanks your explain.
  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    Yes, but again - you cannot read data from the LIDD display when you use DMA mode.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Dear Biser

    Thanks your kind explain, but I still have some questions about PCLK. We test the image from our customer, and their LCD works fine in kernel. I measure the signal of PCLK from u-boot to kernel, when in u-boot, the signal has no change, when it get into kernel, the signal is converted into high. But in our u-boot, the signal just like above, when it get into kernel, the signal is converted into a sin wave, it is not pull high. so I think we must omit some action to led to that their behavior is not the same, as a export of point, could you please direct me where maybe I can to revise them. Thank you again.

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    Please check the waveforms in section 7.10.1 of the AM335X Datasheet Rev. H. You should also have your display datasheet in order to know what signals are required. My suggestion is to start by studying how this display is initialized in the kernel driver, and implement the same mechanism in u-boot.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points
    Dear Biser

    Thank you my friend.
    So except I initiate LCDC and I need to initiate our display as well ? I have ever seen that some initialized code in LCD display datasheet.
  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    Probably yes. These display usually need some initialization before you can write data into their memory.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Hi Biser 

    Now I know I need to initiate registers for LCD panel, but I don't know what API I can use in u-boot to write to register of LCD display.

    Is something like HWREG ?  or use am335x (LCD_HSYNC)write strobe ?   Sorry, this sounds a stupid questions.

  • 0 in reply to Bernie Chen
    Expert 2190 points

    Dear Biser

    If I want transfer a initial command to LCD panel, that I need is LIDD_CS0_ADDR ?  Just like discussing above? HWREG(SOC_LCDC_0_REGS+LIDD_CS0_ADDR)=0xXXX?  Thank you.

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    Generally speaking, yes. But I cannot say anything precisely without knowing what the LCD panel requires and how it's connected to the system.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Dear Biser

    OK,  I really hope you do not mind  I attach some information  to this  about LCD panel, because I now have no idea to do, I need discussing.  

    It looks that have some control signals (CS, WR, RS, RD), and there are explanation of pin description in LCD panel datasheet blew:

       and below is this panel reguires initial code:

                void Initial_DISPLAY_CONTROL(void) {
                      WriteCOM_CN(0x11);
                      delay(20);
                      WriteCOM_CN(0xf0);
                      WriteDAT1_MAIN(0x01);
                      WriteCOM_CN(0xf6);
                      WriteDAT1_MAIN(0x00);
                      WriteCOM_CN(0xB1);
                      WriteDAT1_MAIN(0x01);
                      WriteDAT1_MAIN(0x2c);
                      WriteDAT1_MAIN(0x2d);
                      WriteCOM_CN(0xB2);
                      WriteDAT1_MAIN(0x01);
                      WriteDAT1_MAIN(0x2c);
                      WriteDAT1_MAIN(0x2b);
                      WriteCOM_CN(0xb3);
                      WriteDAT1_MAIN(0x01);
                      WriteDAT1_MAIN(0x2c);
                      WriteDAT1_MAIN(0x2b);
                      WriteDAT1_MAIN(0x01);
                      WriteDAT1_MAIN(0x2c);
                      WriteDAT1_MAIN(0x2b);
                      WriteCOM_CN(0xb4);
                      WriteDAT1_MAIN(0x07);

                             ....

        }

    so that we need to do is add some statement such as HWREG(SOC_LCDC_0_REG + LIDD_CS0_ADDR)=@##$$$  into below pseudo code and adjust timing setting during I transfer command to LCD display?  Thank you.

    //EnableClocks
    wr 006C 0000_0007
    //LCD Control Register
    wr 0004 0000_8000          //set clock divisor
    //LIDD Control Register
    wr 000C 0000_000C          //set output bus polarities and lidd_mode_sel
    //LIDD CS0 Register
    wr 0010 0822_1044          //set bus timing parameters for CS0
    //DMA Control Register
    wr 0040 0000_0030          //set DMA parameters like burst size, memory layout
    //DMA FB0 Base Register
    wr 0044 0000_0004          //DMA start byte address
    //DMA FB0 Ceiling Register
    wr 0048 0000_003C          //DMA end byte address
    //LIDD Control Register - enable DMA
    wr 000C 0000_010C          // Flip LIDD DMA enable bit

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points

    See sections 13.5.1.5 and 13.5.1.6 in the AM335X TRM Rev. L.

    WriteCOM_CN should correspond to writing into LIDD_CS0_ADDR Register.

    WriteDAT1_MAIN should correspond to writing into LIDD_CS0_DATA Register.

    Note that CPU reads and writes to these registers are not permitted if the LIDD module is in DMA mode (cfg_lidd_dma_en = 1). Therefore this write sequence should be done before enabling the DMA.

  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points
    Dear Biser

    Do I need to set LIDD_CS0_CONF register before I Write something to LIDD_CS0_ADDR or LIDD_CS0_DATA?
    Thank you.
  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    Of course, both LIDD_CTRL and LIDD_CS0_CONF should be setup first.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points
    Dear Biser

    When I write something into LIDD_CS0_ADDR or LIDD_CS0_DATA, and it will automatically sent command or data after I do

    wr 000C 0000_010C // Flip LIDD DMA enable bit ??
  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    When you write something into LIDD_CS0_ADDR or LIDD_CS0_DATA it will be sent out directly. When you flip the LIDD DMA enable bit you cannot do this anymore, then data will be sent from the framebuffer via DMA.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Hi Biser 

    Thanks your patient reply, I think I can do some tries.

     

  • 0 in reply to Bernie Chen
    Expert 2190 points

    Hi TI


        HWREG(0x4830E000 + 0x4) = 0x00008000;  
        HWREG(0x4830E000 + 0xc) = 0x0000000c;
        HWREG(0x4830E000 + 0x10) = 0x08221044;

        HWREG(0x4830E000 + 0x14) = 0x11;   /*     LCD panel initial code
        mdelay(20);                                                  

        HWREG(0x4830E000 + 0x14) = 0xf0;
        HWREG(0x4830E000 + 0x18) = 0x01;

        HWREG(0x4830E000 + 0x14) = 0xf6;
        HWREG(0x4830E000 + 0x18) = 0x00;

        HWREG(0x4830E000 + 0x14) = 0xb1;
        HWREG(0x4830E000 + 0x18) = 0x01;
        HWREG(0x4830E000 + 0x18) = 0x2c;
        HWREG(0x4830E000 + 0x18) = 0x2d;

        HWREG(0x4830E000 + 0x14) = 0xb2;
        HWREG(0x4830E000 + 0x18) = 0x01;
        HWREG(0x4830E000 + 0x18) = 0x2c;
        HWREG(0x4830E000 + 0x18) = 0x2b;

        HWREG(0x4830E000 + 0x14) = 0xb3;
        HWREG(0x4830E000 + 0x18) = 0x01;
        HWREG(0x4830E000 + 0x18) = 0x2c;
        HWREG(0x4830E000 + 0x18) = 0x2b;
        HWREG(0x4830E000 + 0x18) = 0x01;
        HWREG(0x4830E000 + 0x18) = 0x2c;
        HWREG(0x4830E000 + 0x18) = 0x2b;

        HWREG(0x4830E000 + 0x14) = 0xb4;
        HWREG(0x4830E000 + 0x18) = 0x07;

        HWREG(0x4830E000 + 0x14) = 0xb6;
        HWREG(0x4830E000 + 0x18) = 0x84;
        HWREG(0x4830E000 + 0x18) = 0xf0;
        HWREG(0x4830E000 + 0x18) = 0x20;

        HWREG(0x4830E000 + 0x14) = 0xc0;
        HWREG(0x4830E000 + 0x18) = 0xa2;
        HWREG(0x4830E000 + 0x18) = 0x02;
        HWREG(0x4830E000 + 0x18) = 0x04;

        HWREG(0x4830E000 + 0x14) = 0xc1;
        HWREG(0x4830E000 + 0x18) = 0xc5;

        HWREG(0x4830E000 + 0x14) = 0xc2;
        HWREG(0x4830E000 + 0x18) = 0x0a;
        HWREG(0x4830E000 + 0x18) = 0x00;

        HWREG(0x4830E000 + 0x14) = 0xc3;
        HWREG(0x4830E000 + 0x18) = 0x8a;
        HWREG(0x4830E000 + 0x18) = 0x2a;

        HWREG(0x4830E000 + 0x14) = 0xc4;
        HWREG(0x4830E000 + 0x18) = 0x8a;
        HWREG(0x4830E000 + 0x18) = 0xee;

        HWREG(0x4830E000 + 0x14) = 0xc5;
        HWREG(0x4830E000 + 0x18) = 0x04;

        HWREG(0x4830E000 + 0x14) = 0x36;
        HWREG(0x4830E000 + 0x18) = 0xc8;

        HWREG(0x4830E000 + 0x14) = 0xe0;
        HWREG(0x4830E000 + 0x18) = 0x0f;
        HWREG(0x4830E000 + 0x18) = 0x1a;
        HWREG(0x4830E000 + 0x18) = 0x0f;
        HWREG(0x4830E000 + 0x18) = 0x18;
        HWREG(0x4830E000 + 0x18) = 0x2f;
        HWREG(0x4830E000 + 0x18) = 0x28;
        HWREG(0x4830E000 + 0x18) = 0x20;
        HWREG(0x4830E000 + 0x18) = 0x22;
        HWREG(0x4830E000 + 0x18) = 0x1f;
        HWREG(0x4830E000 + 0x18) = 0x1b;
        HWREG(0x4830E000 + 0x18) = 0x23;
        HWREG(0x4830E000 + 0x18) = 0x37;
        HWREG(0x4830E000 + 0x18) = 0x00;
        HWREG(0x4830E000 + 0x18) = 0x07;
        HWREG(0x4830E000 + 0x18) = 0x02;
        HWREG(0x4830E000 + 0x18) = 0x10;

        HWREG(0x4830E000 + 0x14) = 0xe1;
        HWREG(0x4830E000 + 0x18) = 0x0f;
        HWREG(0x4830E000 + 0x18) = 0x1b;
        HWREG(0x4830E000 + 0x18) = 0x0f;
        HWREG(0x4830E000 + 0x18) = 0x17;
        HWREG(0x4830E000 + 0x18) = 0x33;
        HWREG(0x4830E000 + 0x18) = 0x2c;
        HWREG(0x4830E000 + 0x18) = 0x29;
        HWREG(0x4830E000 + 0x18) = 0x2e;
        HWREG(0x4830E000 + 0x18) = 0x30;
        HWREG(0x4830E000 + 0x18) = 0x30;
        HWREG(0x4830E000 + 0x18) = 0x39;
        HWREG(0x4830E000 + 0x18) = 0x3f;
        HWREG(0x4830E000 + 0x18) = 0x00;
        HWREG(0x4830E000 + 0x18) = 0x07;
        HWREG(0x4830E000 + 0x18) = 0x03;
        HWREG(0x4830E000 + 0x18) = 0x10;
        HWREG(0x4830E000 + 0x18) = 0x29;                  */

        HWREG(0x4830E000 + 0x40) = 0x00000030;

         I have referenced LCD (st7735r) datasheet, the "RS" pin form LCD display connected with our LCD_VSYNC , we think LCD_VSYNC  should be high when I transfer "data",  if low when I transfer "command", but I measure the signal with LCD_VSYNC, it is keeping low, so I want to know what register can control LCD_VSYNC pin that I can transfer "data"?  Thank you.

      

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points

    Bernie Chen said:
    HWREG(0x4830E000 + 0xc) = 0x0000000c;

    You have selected Hitachi Async mode. I think your display is MPU80 Async.

  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points
    Dear Biser

    Oh, I actually make a serial mistake, I have revise them with HWREG(0x4830E000 + 0xc) = 0x0000000b; , but there still have no screen in LCD display. Do you think should I control timing of (LCD_VSYNC/A0/RS(LCD panel datasheet)) pin when I transfer some initial data which is in LIDD_CS0_DATA? Or LCDC will works automatically when if I want to transfer initial "data"? Thank you.
  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    Yes, you should have the LIDD controller configured before transmitting data.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Hi Biser

    Our customer's image can display screen in LCD in kernel , and we capture their CS signal below,  It is pull high just a moment, and keep low after pulling high.

    Ours in u-boot, and the signal of cs is below

    What it is meaning?  Thank you.

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    Please check Figures 7-78, 7-79 and 7-80 from the AM335X Datasheet Rev. H for the timing diagrams for LIDD 8080 mode.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Hi Biser

    Sorry I don't understand your figure.
    We only have CS0, no have CS1, the figure you imply me that my signal is correct, not like customer's? Please, give me more suggestions.
    I appreciate your support.

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    The chip select signal goes low on each bus transaction. You can disregard CS1 if you don't use it.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Dear Biser 

    I read LCD display datasheet, I know chip select pin is active low, as you talk, that it goes low on each bus transaction. What is confusing me is our signal, it is not keeping low, just like a wave. As result, it can't do bus transaction when edge of high. And customer's signal is keeping low, they are not have same behavior, then CPU can write commands and data to LCD display consistently so that it can show picture in screen. Am I wrong? If I wrong please correct me, thank you.  

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    Have you pinmuxed this pin - LCD_AC_BIAS_EN, to mode 0? The same question applies to all LCD pins you use.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Dear Biser

    I check all of pinmux about LCD pin again.

    All of control SHIFT are 0x00000000u, so LCD_AC_BIAS_EN is mode 0

    LCD_DATA0~LCD_DATA15 are mode 0

    GPMC_AD8~GPMC_AD15 are used by gpio

    LCD_HSYNC, LCD_VSYNC, LCD_PCLK are mode 0

    Is anything weird? Thank you.

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(0)) =
                       (0 << CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_MMODE_SHIFT)    |
                       (1 << CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUDEN_SHIFT)    |
                       (0 << CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUTYPESEL_SHIFT)|
                       (1 << CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RXACTIVE_SHIFT) |
                       (0 << CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(1)) =
                       (0 << CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_MMODE_SHIFT)    |
                       (1 << CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUDEN_SHIFT)    |
                       (0 << CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUTYPESEL_SHIFT)|
                       (1 << CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RXACTIVE_SHIFT) |
                       (0 << CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_SLEWCTRL_SHIFT);  

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(2)) =
                       (0 << CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_MMODE_SHIFT)    |
                       (1 << CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUDEN_SHIFT)    |
                       (0 << CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUTYPESEL_SHIFT)|
                       (1 << CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RXACTIVE_SHIFT) |
                       (0 << CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_SLEWCTRL_SHIFT);  

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(3)) =
                       (0 << CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_MMODE_SHIFT)    |
                       (1 << CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUDEN_SHIFT)    |
                       (0 << CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUTYPESEL_SHIFT)|
                       (1 << CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RXACTIVE_SHIFT) |
                       (0 << CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(4)) =
                       (0 << CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_MMODE_SHIFT)    |
                       (1 << CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUDEN_SHIFT)    |
                       (0 << CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUTYPESEL_SHIFT)|
                       (1 << CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RXACTIVE_SHIFT) |
                       (0 << CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_SLEWCTRL_SHIFT);
     
             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(5)) =
                       (0 << CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_MMODE_SHIFT)    |
                       (1 << CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUDEN_SHIFT)    |
                       (0 << CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUTYPESEL_SHIFT)|
                       (1 << CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RXACTIVE_SHIFT) |
                       (0 << CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(6)) =
                       (0 << CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_MMODE_SHIFT)    |
                       (1 << CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUDEN_SHIFT)    |
                       (0 << CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUTYPESEL_SHIFT)|
                       (1 << CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RXACTIVE_SHIFT) |
                       (0 << CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(7)) =
                       (0 << CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_MMODE_SHIFT)    |
                       (1 << CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUDEN_SHIFT)    |
                       (0 << CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUTYPESEL_SHIFT)|
                       (1 << CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RXACTIVE_SHIFT) |
                       (0 << CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(8)) =
                       (0 << CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_MMODE_SHIFT)    |
                       (1 << CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUDEN_SHIFT)    |
                       (0 << CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUTYPESEL_SHIFT)|
                       (1 << CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RXACTIVE_SHIFT) |
                       (0 << CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(9)) =
                       (0 << CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_MMODE_SHIFT)    |
                       (1 << CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUDEN_SHIFT)    |
                       (0 << CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUTYPESEL_SHIFT)|
                       (1 << CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RXACTIVE_SHIFT) |
                       (0 << CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(10)) =
                     (0 << CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_MMODE_SHIFT)    |
                     (1 << CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUDEN_SHIFT)    |
                     (0 << CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUTYPESEL_SHIFT)|
                     (1 << CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RXACTIVE_SHIFT) |
                     (0 << CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(11)) =
                     (0 << CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_MMODE_SHIFT)     |
                     (1 << CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RXACTIVE_SHIFT)  |
                       (0 << CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(12)) =
                     (0 << CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_MMODE_SHIFT)     |
                     (1 << CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(13)) =
                     (0 << CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_MMODE_SHIFT)     |
                     (1 << CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(14)) =
                     (0 << CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_MMODE_SHIFT)     |
                     (1 << CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(15)) =
                     (0 << CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_MMODE_SHIFT)     |
                     (1 << CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(15) ) =
                     (7 << CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(14) ) =
                     (7 << CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUTYPESEL_SHIFT) |
                     (1<< CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(13) ) =
                     (7 << CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RXACTIVE_SHIFT)  |
                       (0 << CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(12) ) =
                     (7 << CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUTYPESEL_SHIFT) |
                     (1<< CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(11) ) =
                     (7 << CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUTYPESEL_SHIFT) |
                     (1<< CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(10) ) =
                     (7 << CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(9) ) =
                     (7 << CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(8) ) =
                     (7 << CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_VSYNC) =
                     (0 << CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_HSYNC) =
                     (0 << CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_PCLK) =
                     (0 << CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_SLEWCTRL_SHIFT);

             HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_AC_BIAS_EN) =
                     (0 << CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_MMODE_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUDEN_SHIFT)     |
                     (0 << CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUTYPESEL_SHIFT) |
                     (1 << CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RXACTIVE_SHIFT)  |
                     (0 << CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_SLEWCTRL_SHIFT);

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    That's OK then. Do you have the timing diagrams of your display? I suspect that the clock frequency you use is way too high.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Dear Biser

    I reference: e2e.ti.com/.../228047

    When I use HWREG to write some commands for LCD display, and I measure the singal of LCD_VSYNC(RS), it is keeping high.

    I instead of HWREG by "writel" with inital code of LCD display. And I measure the LCD_VSYNC(RS),  there are have signal just like wave.

    I got information from LCD display FAE that if I want to send command, that I need the LCD_VSYNC(RS) active low, and CS active low, so I modify CS0  to mode of gpio which is always low.

    Now, my screen havs something or noises  below:

      

      Probably the signal have not match with timing diagram,  or image raw data not match with this LCD requires (RGB565 or resolution) .

       Dear  Biser, could you help us to find  some where maybe wrong? Thank you.

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points

    Please study carefully Figure 7-78 from the AM335X Datasheet Rev. H. You must configure the LIDD timings so that they match those require by your display, that you posted above. This is done in the LIDD_CS0_CONF register.

  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Dear Biser

    OK, except LIDD_CS0_CONF, you suspect clock frequence that too high, where I can tune it?

    HWREF(0x4830E000 + 0x6c) = 0x00000007 //enable LIDD, Core, Raster
    HWREG(0x4830E000 + 0x4) = 0x00008000; // This is I found the relation code with frequence

    And I call FAE with LCD display, he says  that our LCD panel has start up, but there are no data it can read, so LCD has a lot of noises. But I measure, LCD_DATA0~LCD_DATA15 are having signal.

    Thank you.

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points

    Bernie Chen said:
    HWREG(0x4830E000 + 0x4) = 0x00008000; // This is I found the relation code with frequence

    This is where the clock divisor is. You have set it to 0x80, which would give you 192MHz / 128 = 1.5MHz MCLK. All LIDD timings are given in number of MCLK cycles.

  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Dear Biser

    I use Async mode , it would perform no MCLK  function, so I set CLKDIV has no effect for all of timings setting??? And  our LCD_MEM_CLK  pin doesn't be pulled.  Thank you.

  • 0 in reply to Bernie Chen
    Expert 2190 points

    Dear Biser

    FAE of LCD display tell me that I lost the last command, so I added it. Finally, I can see picture in u-boot.

    But this is so weird! I comment out  

             HWREG(SOC_LCDC_0_REG + LCDC_LCDDMA_FB0_BASE) =  base;
             HWREG(SOC_LCDC_0_REG + LCDC_LCDDMA_FB0_CEILING) = ceiling;

             HWREG(0x4830E000 + 0xc) = 0x00000103

       I just do 

                    LCD pinmux setting()

                    HWREG(0x4830E000 + 0x4) = 0x00008000; //setting CLKDIV
                    HWREG(0x4830E000 + 0xc) = 0x00000003; //enable async 8080

                     initial LCD code()


    Because I have comment out the codes about frambuffer so that DMA engine can't  read raw data from FB0 and transfer our raw data from FB0, but I measure LCD_DATA0~15 they have signal, and the TI picture is appeared below:

      Where the picture in u-boot? And where DMA engine do transfer from framebuffer to LIDD interface? Thank you.

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    Do you do this from cold start (power off)? If not, there could be a fragment of the picture in the display's memory.

    Regarding your previous post, you may not use MCLK externally, but this is still the clock used by the LIDD controller internally and all LIDD interface timings are derived from it.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Dear Biser

    OK, thanks your explanation about MCLK.  And I use cold start again and again.

    I  can't believe my eye, I am not to revise any code, and the picture is changed below. I measure the LCD_HSYNC(WR) & LCD_DATA0~15, they have signal just like DMA engine has action about capture data to LIDD interface.

  • 0 in reply to Bernie Chen
    Expert 2190 points
    Dear Biser

    FAE says the display actually has memory like you say, and maybe I use customer image in kernel let picture left in memory.
  • 0 in reply to Bernie Chen
    Expert 2190 points

    Dear Biser

    I have the same question above, does DMA engine  able to transfer data from frame buffer to LIDD output using 8 bit?

     

    This is from AM335x TRM

    "The DMA module requires the start and end DDR addresses to be on word-aligned byte addresses. The
    MPU/LIDD bus is a halfword (16 bit) output, so both the upper and lower halfwords of the DDR memory
    will be sent out. Thus, the number of data elements sent to the LIDD by the DMA must always result in an
    even number of bus MPU bus transactions. In other words, a transfer of three 32-bit words from DDR will
    result in six 16-bit bus transactions."

    Because our LCD display controller need 8-bit data input

    Thank you.

     

  • 0 in reply to Bernie Chen
    TI__Guru**** 393215 points
    Why don't you try to send out the image by MPU writes first, to confirm that everything else is working? For DMA mode you may need to pad the image data with empty bytes, so that is conforms to the 16-bit requirement.
  • 0 in reply to Biser Gatchev-XID
    Expert 2190 points

    Dear Biser


    I really appreciate your help, thank you.

  • 0 in reply to Bernie Chen
    Prodigy 130 points
    HI,

    I have fallowed above procedure to enable lidd mode for my display but i am facing the issue while booting

    U-Boot 2013.10-00189-g78d8ebd-dirty (Aug 03 2015 - 13:46:03)

    I2C: ready
    DRAM: 256 MiB
    mycode start here
    Lcd_Init:before Setup lcd
    mycode start here
    data abort

    MAYBE you should read doc/README.arm-unaligned-accesses

    pc : [<8f46c1a8>] lr : [<8f46c1a0>]
    sp : 8f02df00 ip : 00000000 fp : 80614bd0
    r10: 80945ed2 r9 : 8f02df38 r8 : 4030cdcc
    r7 : 4030cb7c r6 : 00000002 r5 : 8f79cdd7 r4 : 4830e000
    r3 : 8f4780e4 r2 : 00000001 r1 : 0000000a r0 : 00000013
    Flags: nZCv IRQs off FIQs on Mode SVC_32
    Resetting CPU ...

    resetting ...

    please guide me .