Hi,
We are working on a custom board design with the memory setup lifted from the AM437x IDK reference design. I've extracted the configuration parameters for the EMIF registers from the IDK and am using those values as a reference. U-Boot does the following:
===
/* MT41K256M16HA-125 run in 1.5V compatibility mode */
/* Since this chip is used in the IDK reference design, these are the
values from the IDK SDK's bootloader setup code */
const struct emif_regs ddr3_emif_regs_400Mhz_idk = {
.sdram_config = 0x61A11B32,
.ref_ctrl = 0x00000C30,
.sdram_tim1 = 0xEAAAD4DB,
.sdram_tim2 = 0x266B7FDA,
.sdram_tim3 = 0x107F8678,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074BE4,
.temp_alert_config = 0x0,
.emif_ddr_phy_ctlr_1 = 0x00008009,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x00700070,
.emif_ddr_ext_phy_ctrl_3 = 0x00700070,
.emif_ddr_ext_phy_ctrl_4 = 0x00700070,
.emif_ddr_ext_phy_ctrl_5 = 0x00700070,
.emif_rd_wr_exec_thresh = 0x00000405,
.emif_prio_class_serv_map = 0x00000000,
.emif_connect_id_serv_1_map = 0x00000000,
.emif_connect_id_serv_2_map = 0x00000000,
.emif_cos_config = 0x00FFFFFF
};
// according to the docs, these are mostly ignored in the DDR3 case,
// yet the code needs them else it does not compile.
const u32 ext_phy_ctrl_const_base_ddr3_idk[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00700070,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00340034,
0x00340034,
0x00340034,
0x00340034,
0x00340034,
0x00000000,
0x00600020,
0x40010080,
0x08102040
};
// and then there is some other not relevant code
void sdram_init(void)
{
enable_vtt_regulator();
do_sdram_init(&ioregs_ddr3, &ddr3_emif_regs_400Mhz_idk,
ext_phy_ctrl_const_base_ddr3_idk,
EMIF_SDRAM_TYPE_DDR3);
}
===
Also, since our traces are shorter, I've adjusted the output impedance defines accordingly:
===
#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x86 #define DDR3_DATA0_IOCTRL_VALUE 0x86 #define DDR3_DATA1_IOCTRL_VALUE 0x86 #define DDR3_DATA2_IOCTRL_VALUE 0x86 #define DDR3_DATA3_IOCTRL_VALUE 0x86
===
However, despite all this, I still get lockups, data aborts, and memory errors in U-Boot's memory tests. Errors are of this type:
===
Mem error @ 0x900B5A5C: found 5A4EFFBF, expected 5A4EFFFF Mem error @ 0x90685A5C: found 59F1FFBF, expected 59F1FFFF Mem error @ 0x90905A5C: found 59C9FFBF, expected 59C9FFFF
===
Which suggests something amiss with bit 6. I've seen similar errors which suggest something amiss with bit 21. However, it cannot be a short because it is not consistently that value, which suggests something related to timing. At first, I thought about mismatched trace lengths or impedance, but I asked our layout engineer, and he checked the design and says that:
- Each byte is routed through a different layer, but all bits in a byte are together.
- All lines were specified to be impedance matched.
- All lines are withing 25 mils of each other.
Does anyone have any suggestions as to what to look at next? Suggestions are appreciated. Thanks in advance.
