Hello, I need help getting this emmc module to work on my custom board. Attached are my am335x_evm.h config, board.c and mux.c files.
Its a 4GB module connected to mmc1. I think I got the pinmux right.
I'm not sure what else am I missing in my config file but I got this message when u-boot is loaded.
Unrecognized filesystem type.
I loaded the kernel and it also can't find the filesystems
Any help is much appreciated.
board.c
/* * board.c * * Board functions for TI AM335X based boards * * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <errno.h> #include <spl.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> #include <asm/arch/omap.h> #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> #include <asm/io.h> #include <asm/emif.h> #include <asm/gpio.h> #include <i2c.h> #include <miiphy.h> #include <cpsw.h> #include <power/tps65217.h> #include <power/tps65910.h> #include <environment.h> #include <watchdog.h> #include <environment.h> #include "board.h" DECLARE_GLOBAL_DATA_PTR; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; #ifndef CONFIG_SKIP_LOWLEVEL_INIT static const struct ddr_data ddr3_data = { .datardsratio0 = AS4C128M16D3_RD_DQS, .datawdsratio0 = AS4C128M16D3_WR_DQS, .datafwsratio0 = AS4C128M16D3_PHY_FIFO_WE, .datawrsratio0 = AS4C128M16D3_PHY_WR_DATA, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = AS4C128M16D3_RATIO, .cmd0iclkout = AS4C128M16D3_INVERT_CLKOUT, .cmd1csratio = AS4C128M16D3_RATIO, .cmd1iclkout = AS4C128M16D3_INVERT_CLKOUT, .cmd2csratio = AS4C128M16D3_RATIO, .cmd2iclkout = AS4C128M16D3_INVERT_CLKOUT, }; static struct emif_regs ddr3_emif_reg_data = { .sdram_config = AS4C128M16D3_EMIF_SDCFG, .ref_ctrl = AS4C128M16D3_EMIF_SDREF, .sdram_tim1 = AS4C128M16D3_EMIF_TIM1, .sdram_tim2 = AS4C128M16D3_EMIF_TIM2, .sdram_tim3 = AS4C128M16D3_EMIF_TIM3, .zq_config = AS4C128M16D3_ZQ_CFG, .emif_ddr_phy_ctlr_1 = AS4C128M16D3_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN, }; #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { /* break into full u-boot on 'c' */ if (serial_tstc() && serial_getc() == 'c') return 1; #ifdef CONFIG_SPL_ENV_SUPPORT env_init(); env_relocate_spec(); if (getenv_yesno("boot_os") != 1) return 1; #endif /* CONFIG_SPL_ENV_SUPPORT */ return 0; } #endif /* CONFIG_SPL_OS_BOOT */ #define OSC (V_OSCK/1000000) const struct dpll_params dpll_ddr = { 400, OSC-1, 1, -1, -1, -1, -1}; void am33xx_spl_board_init(void) { int mpu_vdd; /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); } const struct dpll_params *get_dpll_ddr_params(void) { enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); return &dpll_ddr; } void set_uart_mux_conf(void) { #ifdef CONFIG_SERIAL1 enable_uart0_pin_mux(); #endif /* CONFIG_SERIAL1 */ #ifdef CONFIG_SERIAL2 enable_uart1_pin_mux(); #endif /* CONFIG_SERIAL2 */ #ifdef CONFIG_SERIAL3 enable_uart2_pin_mux(); #endif /* CONFIG_SERIAL3 */ #ifdef CONFIG_SERIAL4 enable_uart3_pin_mux(); #endif /* CONFIG_SERIAL4 */ #ifdef CONFIG_SERIAL5 enable_uart4_pin_mux(); #endif /* CONFIG_SERIAL5 */ #ifdef CONFIG_SERIAL6 enable_uart5_pin_mux(); #endif /* CONFIG_SERIAL6 */ } void set_mux_conf_regs(void) { __maybe_unused struct am335x_baseboard_id header; // if (read_eeprom(&header) < 0) // puts("Could not get board ID mux.\n"); enable_board_pin_mux(&header); } const struct ctrl_ioregs ioregs = { .cm0ioctl = AS4C128M16D3_IOCTRL_VALUE, .cm1ioctl = AS4C128M16D3_IOCTRL_VALUE, .cm2ioctl = AS4C128M16D3_IOCTRL_VALUE, .dt0ioctl = AS4C128M16D3_IOCTRL_VALUE, .dt1ioctl = AS4C128M16D3_IOCTRL_VALUE, }; void sdram_init(void) { config_ddr(400, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ /* * Basic board specific setup. Pinmux has been handled already. */ int board_init(void) { #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif /* CONFIG_HW_WATCHDOG */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NOR) || defined(CONFIG_NAND) gpmc_init(); #endif /* CONFIG_NOR || CONFIG_NAND */ return 0; } #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG char safe_string[HDR_NAME_LEN + 1]; char name[] = "StackHub"; char version[] = "1.00"; /* Now set variables based on the header. */ strncpy(safe_string, (char *)name, sizeof(name)); safe_string[sizeof(name)] = 0; setenv("board_name", "StackHub"); strncpy(safe_string, (char *)version, sizeof(version)); safe_string[sizeof(version)] = 0; setenv("board_rev", "1.00"); #endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */ return 0; } #endif /* CONFIG_BOARD_LATE_INIT */ #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) static void cpsw_control(int enabled) { /* VTP can be added here */ return; } static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, #ifdef CONFIG_PHY_NATSEMI .phy_addr = 1, #else .phy_addr = 0, #endif /* CONFIG_PHY_NATSEMI */ }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, .phy_addr = 1, }, }; static struct cpsw_platform_data cpsw_data = { .mdio_base = CPSW_MDIO_BASE, .cpsw_base = CPSW_BASE, .mdio_div = 0xff, .channels = 8, .cpdma_reg_ofs = 0x800, .slaves = 1, .slave_data = cpsw_slaves, .ale_reg_ofs = 0xd00, .ale_entries = 1024, .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, }; #endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */ /* * This function will: * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr * in the environment * Perform fixups to the PHY present on certain boards. We only need this * function in: * - SPL with either CPSW or USB ethernet support * - Full U-Boot, with either CPSW or USB ethernet * Build in only these cases to avoid warnings about unused variables * when we build an SPL that has neither option but full U-Boot will. */ #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ && defined(CONFIG_SPL_BUILD)) || \ ((defined(CONFIG_DRIVER_TI_CPSW) || \ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ !defined(CONFIG_SPL_BUILD)) int board_eth_init(bd_t *bis) { int rv, n = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; __maybe_unused struct am335x_baseboard_id header; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); } #ifdef CONFIG_DRIVER_TI_CPSW mac_lo = readl(&cdev->macid1l); mac_hi = readl(&cdev->macid1h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!getenv("eth1addr")) { if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("eth1addr", mac_addr); } writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; puts("eth: PHY-RMII\n"); rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; #endif /* CONFIG_DRIVER_TI_CPSW */ #endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */ return n; } #endif
mux.c
/* * mux.c * * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <common.h> #include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> #include <asm/arch/mux.h> #include <asm/io.h> #include <i2c.h> #include "board.h" static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ {-1}, }; static struct module_pin_mux uart1_pin_mux[] = { {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ {-1}, }; static struct module_pin_mux uart2_pin_mux[] = { {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ {-1}, }; static struct module_pin_mux uart3_pin_mux[] = { {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ {-1}, }; static struct module_pin_mux uart4_pin_mux[] = { {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ {-1}, }; static struct module_pin_mux uart5_pin_mux[] = { {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ {-1}, }; static struct module_pin_mux mmc1_pin_mux[] = { {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ {-1}, }; static struct module_pin_mux i2c0_pin_mux[] = { {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ {-1}, }; static struct module_pin_mux i2c1_pin_mux[] = { {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ {-1}, }; static struct module_pin_mux rmii1_pin_mux[] = { {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RX_ERR */ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TX_EN */ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REF_CLK */ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ {-1}, }; #ifdef CONFIG_NAND static struct module_pin_mux nand_pin_mux[] = { {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ #endif {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */ {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ {-1}, }; #elif defined(CONFIG_NOR) static struct module_pin_mux bone_norcape_pin_mux[] = { {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */ {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */ {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */ {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */ {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */ {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */ {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */ {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */ {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */ {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */ {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */ {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */ {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */ {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */ {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */ {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */ {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */ {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */ {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */ {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */ {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */ {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */ {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */ {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */ {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */ {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */ {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */ {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */ {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */ {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/ {-1}, }; #endif #if defined(CONFIG_NOR_BOOT) void enable_norboot_pin_mux(void) { configure_module_pin_mux(bone_norcape_pin_mux); } #endif void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); } void enable_uart1_pin_mux(void) { configure_module_pin_mux(uart1_pin_mux); } void enable_uart2_pin_mux(void) { configure_module_pin_mux(uart2_pin_mux); } void enable_uart3_pin_mux(void) { configure_module_pin_mux(uart3_pin_mux); } void enable_uart4_pin_mux(void) { configure_module_pin_mux(uart4_pin_mux); } void enable_uart5_pin_mux(void) { configure_module_pin_mux(uart5_pin_mux); } void enable_i2c0_pin_mux(void) { configure_module_pin_mux(i2c0_pin_mux); } void enable_board_pin_mux(struct am335x_baseboard_id *header) { /* AM335x Stack Hub */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(rmii1_pin_mux); configure_module_pin_mux(mmc1_pin_mux); }