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AM3703 - failure to boot, cannot read registers

Kyle Mouratidis
Prodigy 150 points
Other Parts Discussed in Thread: AM3703, TPS65951

Hi there,

I'm attempting to debug an AM3703CUSD100 with the XDS100v2 probe in CCS 6.1.  The AM3703 is failing to boot from MMC1 with SYS_BOOT[5:0] = 0b101111.  I have looked at the tracing vectors and confirmed that the ROM attempted to boot from MMC1, but failed.  When I try to look at one of the MMC1 registers, the value shows as "Error: unable to read".  I thought that this may be because of a power domain/clock problem, but wouldn't MMC1 have to be powered and clocked as the ROM attempts to boot from it?

Possibly related - I have encountered an ST processor where I had to edit an xml file to make some registers readable by the debugger.

Any insight on the register problem (or the boot problem) would be appreciated!

Kyle

  • 0
    TI__Guru**** 393215 points
    Hi Kyle,

    I will ask the factory experts to help on this.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru 68890 points
    Kyle, do you have power on vdds_mmc1 while the ROM is trying to boot? The ROM expects power to be supplied to this and the SD card, it does not have control over this.

    Regards,
    James
  • 0 in reply to JJD
    Prodigy 150 points
    Hi James and Biser,

    I have measured vdds_mmc1 to be 3.0V. It is being supplied by the TPS65951 PMIC. I've also probed the MMC1 signals during the Sitara's cold boot and I'm seeing about 100ms of activity on the clock and command lines. Following that, there is a few milliseconds of activity on data0, and then there is nothing else. When I then take a look at the cold boot tracing vector over JTAG, it verifies that the Sitara attempted to boot from MMC1 but the boot failed.

    Thanks,

    Kyle
  • 0 in reply to JJD
    Prodigy 150 points
    Another update:

    I have decoded the last commands that happen on the MMC1 interface before all activity on the interface is terminated:

    CMD4: host sends information to configure the driver stage of the card. Clock rate changes from 400kHz to 12MHz.
    R1: card sends normal response.
    CMD7: host selects the card and puts it into the data transfer state.
    R1: card sends normal response.
    CMD16: host sets the block size for data transfers to 512 bytes.
    R1: card sends normal response.
    CMD55: host tells the card to interpret the next command as application-specific.
    R1: card sends normal response.
    ACMD51: host requests the card’s SCR.
    R1: card sends normal response.
    CMD17: host requests to read the block with starting address 0x00000000.
    R1: card sends normal response.
    Following this response, there is activity on DAT0 for about 350us (512 bytes + CRC).
    CMD17: host requests to read the block with starting address 0x00000020.
    R1: card sends normal response.
    Following this response, there is activity on DAT0 for about 350us (512 bytes + CRC).
    CMD17: host requests to read the block with starting address 0x00000000.
    R1: card sends normal response.
    Following this response, there is activity on DAT0 for about 350us (512 bytes + CRC).
    CMD17: host requests to read the block with starting address 0x00002000.
    R1: card sends normal response.
    Following this response, there is activity on DAT0 for about 350us (512 bytes + CRC).
    CMD17: host requests to read the block with starting address 0x007A2FFF.
    R1: card sends normal response.
    Following this response, there is activity on DAT0 for about 350us (512 bytes + CRC).

    After this block read, there is no further activity on the MMC1 interface.

    Our client has supplied the micro SD card preloaded with the boot files - could this still be a hardware problem, or is it more likely that there is a problem with the SD card or the boot files?

    Thanks,

    Kyle