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AM437x DDR3 Compliance test

shigehiro tsuda
Mastermind 9490 points

Hi,

A compliance test of DDR3 of AM437x fails in the following items.

tCK(avg) Rising Edge Measurements

fail :2.496 ns  -0.5 % 2.500 ns <= VALUE <= 3.300 ns

Try the following:

1. Change impedance and a through rate of CK/CK# in Table 7-287.CTRL_DDR_ADDRCTRL_IOCTRL registers of TRM.
2. Exclude terminal resistance of CK/CK# and raise the reflection of the pattern on purpose.

refclk is 24MHz.

set register of the DPLL DDR is as follows: 

6.13.8.36 PRCM_CM_CLKSEL_DPLL_DDR Register (Offset = 5ACh) :0x00003202

6.13.8.37 PRCM_CM_DIV_M2_DPLL_DDR Register (Offset = 5B0h) :0x00000221
6.13.8.38 PRCM_CM_DIV_M4_DPLL_DDR Register (Offset = 5B8h) :0x00000222

What kind of thing is necessary so that tck(avg) becomes by all means than 2.5ns?

Best Regards,

Shigehiro Tsuda

  • 0
    TI__Guru**** 393215 points
    Hi,
    What software are you using?
  • 0 in reply to Biser Gatchev-XID
    TI__Guru**** 393215 points
    Several things that you should check - 24MHz crystal accuracy, is PLL locked, is spread-spectrum enabled?
  • 0 in reply to Biser Gatchev-XID
    Mastermind 9490 points

    Hi Biser,

    Thank you for your quick reply.

    I reply your several question.

    1.What software are you using?

    ans.

    My customer uses ti-sdk-am437x-evm-08.00.00.00.

    2.24MHz crystal accuracy

    ans.

    24MHz crystal accuracy is good.

    I confirm that the wave pattern of the 24MHz crystal satisfies specifications of Table 5-13 OSC0 Crystal Circuit Requirements of the data sheet in the measurement wave pattern with the oscilloscope.

    24MHz crystal uses SG-210STF of SEIKO EPSON CORPORATION.

    3.is PLL locked

    ans

    Yes,PLL is locked.

    4.is spread-spectrum enabled?

    ans

    The spread-spectrum is disabled.

    Will there be any other information?

    Best Regards,

    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru**** 393215 points
    I have asked the factory team to check possible reasons for this behavior.
  • 0 in reply to Biser Gatchev-XID
    TI__Genius 9485 points
    - Can you share the JEDEC compliance test?
    - Where did you measure the CK/CK# for the test?
    - Can you share the schematics/layout?
    - Is the layout compliant to the DDR3 routing guidelines as listed in the Data sheet?

    Regards, Siva
  • 0 in reply to sivak
    Mastermind 9490 points
    Hi sivak,

    Thank you for your quick reply.
    It is difficult to share the JEDEC compliance test and schematic / layout at e2e site.
    Because these data can not open.

    Is it not avoided by any software correspondence?

    Best Regards,
    Shigeiro Tsuda
  • 0 in reply to shigehiro tsuda
    TI__Genius 9485 points
    Unfortunately, I'm not sure if we can comment much without looking through the details. We obtained your contact information through our FAE team and will contact you directly regarding the reports.

    Meanwhile, please also check the following:

    - Can you verify the connection of the VSS_OSC pin? Is this connected directly to VSS (or) routed as a Kelvin ground?
    - Did you measure the power supply noise on the VDDS_DDR power supply close to the processor? If so, is the supply within expected operating range?
    - Can you confirm if you use parallel termination for the clock? Where did you take the measurement for the DDR3 compliance test?

    Regards, Siva