no HDMi output on Am437x Rico Board

Hi,

This is a third-party board. What software version are you using?

Like I pointed above, this is a third-party board and I am not sure whether it uses the same HDMI encoder as the one used on the TI AM437X GP EVM. You can find information how to configure the HDMI with the TI Linux SDK here: http://processors.wiki.ti.com/index.php/Linux_Core_LCD_Controller_User_Guide The latest release of the Linux SDK can be found here: http://software-dl.ti.com/sitara_linux/esd/processor-sdk/PROCESSOR-SDK-LINUX-AM437X/latest/index_FDS.html

dear Yordan,

thanks you for your support.

I try to change the dts file as below but no HDMI output :( . are there any mistakes in my dts file ?

/dts-v1/;

#include "am4372.dtsi"
#include <dt-bindings/pinctrl/am43xx.h>
#include <dt-bindings/pwm/pwm.h>

/ {
model = "MYIR Rico Board";
compatible = "myir,ricoboard","ti,am4372","ti,am43";

vmmcsd_fixed: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
};

evm_v3p3: tps63031 {
compatible = "regulator-fixed";
regulator-name = "evm_v3p3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};

aliases {
display0 = &lcd0;
display1 = &hdmi0;
};

lcd0: display@0 {
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
video-source = <&dpi>;
data-lines = <24>;
panel-timing {
clock-frequency = <36000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <210>;
hback-porch = <1>;
hsync-len = <43>;
vback-porch = <1>;
vfront-porch = <22>;
vsync-len = <22>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};

/* 4.3 inch, 480x272 resolution LCD, MYiR */
/* lcd0: display@0 {
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
video-source = <&dpi>;
data-lines = <24>;
panel-timing {
clock-frequency = <9600000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <2>;
hback-porch = <2>;
hsync-len = <41>;
vback-porch = <2>;
vfront-porch = <2>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
*/

/*
hdmi0: connector@1 {
compatible = "ti,hdmi_connector";
video-source = <&sii9022>;
};
*/
hdmi0: connector@1 {
compatible = "ti,hdmi_connector";
label = "hdmi";

type = "b";

port {
hdmi_connector_in: endpoint {
remote-endpoint = <&sii9022_out>;
};
};
};

sound {
compatible = "ti,da830-evm-audio";
ti,model = "AM437x-GP-EVM";
ti,audio-codec = <&tlv320aic3106>;
ti,mcasp-controller = <&mcasp1>;
ti,codec-clock-rate = <12000000>;
ti,audio-routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In";
};

/* Gpio keys, MYiR */
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;

user_key1 {
label = "user_key1";
gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>;
linux,code = <102>;
gpio-key,wakeup;
};

user_key2 {
label = "user_key2";
gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
linux,code = <158>;
gpio-key,wakeup;
};
};

/* Gpio leds, MYiR */
gpio-leds {
compatible = "gpio-leds";

status_led0 {
label = "status_led0";
gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};

status_led1 {
label = "status_led1";
gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
default-state = "off";
};

status_led2 {
label = "status_led2";
gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
default-state = "off";
};

status_led3 {
label = "status_led3";
gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};

backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <1>;
};

cpus {
cpu@0 {
cpu0-supply = <&dcdc2>;
};
};
};

&am43xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&clkout2_pin &ddr3_vtt_toggle_default>;
pinctrl-1 = <&clkout1_pin>;

i2c1_pins_default: i2c1_pins_default {
pinctrl-single,pins = <
0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
>;
};

i2c1_pins_sleep: i2c1_pins_sleep {
pinctrl-single,pins = <
0x15c (PIN_INPUT_PULLUP | MUX_MODE7)
0x158 (PIN_INPUT_PULLUP | MUX_MODE7)
>;
};

cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
>;
};

cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};

davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};

davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};

mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x0f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0x0f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0x0f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};

mmc1_sleep_pins: pinmux_mmc1_sleep_pins {
pinctrl-single,pins = <
0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
>;
};

emmc_pins: pinmux_emmc_pins {
pinctrl-single,pins = <
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
>;
};

ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
pinctrl-single,pins = <
0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */
>;
};

i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};

i2c1_pins: i2c1_pins {
pinctrl-single,pins = <
0x240 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* i2c1_scl */
0x248 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* i2c1_sda */
>;
};

dss_pinctrl_default: dss_pinctrl_default {
pinctrl-single,pins = <
0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* GPIO 5_8 to select LCD / HDMI */
>;
};

dss_pinctrl_sleep: dss_pinctrl_sleep {
pinctrl-single,pins = <
0x020 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)
0x024 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)
0x028 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)
0x02C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)
0x030 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)
0x034 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)
0x038 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)
0x03C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)
0x0A0 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x0A4 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x0A8 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x0AC (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x0B0 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x0B4 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x0B8 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x0BC (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)
0x0C0 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)
0x0C4 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x0C8 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)
0x0CC (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)
0x0D0 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x0D4 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x0D8 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)
0x0DC (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)
0x0E0 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)
0x0E4 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)
0x0E8 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x0EC (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)
0x238 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
>;
};

ecap0_pins: backlight_pins {
pinctrl-single,pins = <
0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
>;
};

pixcir_ts_pins: pixcir_ts_pins {
pinctrl-single,pins = <
0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
>;
};

clkout2_pin: clkout2_pin {
pinctrl-single,pins = <
0x274 (PIN_OUTPUT_PULLUP | MUX_MODE3)
>;
};

clkout1_pin: clkout1_pin {
pinctrl-single,pins = <
0x270 (PIN_OUTPUT_PULLUP | MUX_MODE3)
>;
};

dcan0_default: dcan0_default_pins {
pinctrl-single,pins = <
0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
>;
};

dcan1_default: dcan1_default_pins {
pinctrl-single,pins = <
0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.d_can1_tx */
0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
>;
};

mcasp1_pins: mcasp1_pins {
pinctrl-single,pins = <
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
>;
};

mcasp1_sleep_pins: mcasp1_sleep_pins {
pinctrl-single,pins = <
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};

nand_flash_x8: nand_flash_x8 {
pinctrl-single,pins = <
0x26C(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};

uart0_pins: uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};

tsl2550: tsl2550@39 {
compatible = "taos,tsl2550";
reg = <0x39>;
};

tmp275: tmp275@48 {
compatible = "ti,tmp275";
reg = <0x48>;
};

vpfe0_pins_default: vpfe0_pins_default {
pinctrl-single,pins = <
/*0x270 (PIN_OUTPUT_PULLUP | MUX_MODE3) */ /* xdma_event_intr0.clkout1 mode 3*/
0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
0x1B8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/
0x1BC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/
0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
>;
};

vpfe0_pins_sleep: vpfe0_pins_sleep {
pinctrl-single,pins = <
0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
0x1B8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_field mode 0*/
0x1BC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_wen mode 0*/
0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
>;
};

vpfe1_pins_default: vpfe1_pins_default {
pinctrl-single,pins = <
/* 0x270 (PIN_OUTPUT_PULLUP | MUX_MODE3) */ /* xdma_event_intr0.clkout1 mode 3*/
0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
0x1E0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_field mode 0*/
0x1E4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_wen mode 0*/
0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
>;
};

vpfe1_pins_sleep: vpfe1_pins_sleep {
pinctrl-single,pins = <
0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
0x1E0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_field mode 0*/
0x1E4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_wen mode 0*/
0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
>;
};

/* Qspi, MYiR */
qspi1_default: qspi1_default {
pinctrl-single,pins = <
0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
>;
};

/* eeprom, MYiR */
eeprom_wp_pin: eeprom_wp_pin {
pinctrl-single,pins = <
0x2a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)
>;
};
};

&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <100000>;

/* Set OPP50 (0.95V) for VDD MPU and core */
sleep-sequence = /bits/ 8 <
0x02 0x24 0x10 0x6b /* Password unlock 1 */
0x02 0x24 0x16 0x8A /* Set DCDC1 (Core) to 0.95V */
0x02 0x24 0x10 0x67 /* Password unlock 3 */
0x02 0x24 0x1A 0x86 /* Apply DCDC changes */
>;

/* Set OPP100 (1.10V) for VDD core */
wake-sequence = /bits/ 8 <
0x02 0x24 0x10 0x6B /* Password unlock 2 */
0x02 0x24 0x16 0x99 /* Set DCDC1 (Core) to 1.1V */
0x02 0x24 0x10 0x67 /* Password unlock 3 */
0x02 0x24 0x1A 0x86 /* Apply DCDC changes */
>;

tps65218: tps65218@24 {
reg = <0x24>;
compatible = "ti,tps65218";
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;

dcdc1: regulator-dcdc1 {
compatible = "ti,tps65218-dcdc1";
/* VDD_CORE voltage limits min of OPP50 and max of OPP100 */
regulator-name = "vdd_core";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <1144000>;
regulator-boot-on;
regulator-always-on;
};

dcdc2: regulator-dcdc2 {
compatible = "ti,tps65218-dcdc2";
/* VDD_MPU voltage limits min of OPP50 and max of OPP_NITRO */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <1378000>;
regulator-boot-on;
regulator-always-on;
};

dcdc3: regulator-dcdc3 {
compatible = "ti,tps65218-dcdc3";
};

ldo1: regulator-ldo1 {
compatible = "ti,tps65218-ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};

/* MYIR, for usb vbus control */
ls2: regulator-ls2 {
compatible = "ti,tps65218-ls2";
regulator-name = "vdd_vbus0";
};
ls3: regulator-ls3 {
compatible = "ti,tps65218-ls3";
regulator-name = "vdd_vbus1";
regulator-boot-on;
};
};
};

&i2c1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_default>;
pinctrl-1 = <&i2c1_pins_sleep>;
sii9022: sii9022@3b {
#sound-dai-cells = <0>;
compatible = "sil,sii9022";
reg = <0x3b>;

/*
i2s-fifo-routing = <
(ENABLE_BIT|CONNECT_SD0)
0
0
0
>;
*/
};
tlv320aic3106: tlv320aic3106@1b {
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";

/* Regulators */
AVDD-supply = <&evm_v3p3>;
IOVDD-supply = <&evm_v3p3>;
DRVDD-supply = <&evm_v3p3>;
DVDD-supply = <&ldo1>;

};

ov2659@30 {
compatible = "ti,ov2659";
reg = <0x30>;

port {
ov2659_0: endpoint {
remote-endpoint = <&vpfe1_ep>;
mclk-frequency = <12000000>;
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;

sii9022_in: endpoint {
remote-endpoint = <&dpi_out>;
};
};

port@1 {
reg = <1>;

sii9022_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};

&rtc {
status = "okay";
};

&gpio0 {
status = "okay";
};

/* Added by MYiR for GPIO1 & GPIO2 */
&gpio1 {
status = "okay";
};

&gpio2 {
status = "okay";
};

&gpio3 {
status = "okay";
};

&gpio4 {
status = "okay";
};

&gpio5 {
status = "okay";
ti,no-reset;
};

/* Enable qspi, 16MB S25FL128S norflash, MYiR */
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi1_default>;

qspi-gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
spi-max-frequency = <24000000>;
m25p80@0 {
compatible = "s25fl128s";
spi-max-frequency = <24000000>;
reg = <0>;
spi-cpol;
spi-cpha;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
#address-cells = <1>;
#size-cells = <1>;

/* MTD partition table.
* The ROM checks the first 512KiB
* for a valid file to boot(XIP).
*/
partition@0 {
label = "QSPI.U_BOOT";
reg = <0x00000000 0x000080000>;
};
partition@1 {
label = "QSPI.U_BOOT.backup";
reg = <0x00080000 0x00080000>;
};
partition@2 {
label = "QSPI.U_BOOT_ENV";
reg = <0x00100000 0x00020000>;
};
partition@3 {
label = "QSPI.U-BOOT-ENV.backup";
reg = <0x00120000 0x00020000>;
};
partition@4 {
label = "QSPI.U-BOOT-DEVICETREE";
reg = <0x00140000 0x00010000>;
};
partition@5 {
label = "QSPI.KERNEL";
reg = <0x00150000 0x0500000>;
};
partition@6 {
label = "QSPI.FILESYSTEM";
reg = <0x00650000 0x9B0000>;
};
};
};

&dpi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dss_pinctrl_default>;
pinctrl-1 = <&dss_pinctrl_sleep>;
};

&mac {
slaves = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};

&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};

&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii";
};

&mmc2 {
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <8>;
ti,non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins>;
status = "okay";
};

&mmc1 {
status = "okay";
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <4>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mmc1_pins>;
pinctrl-1 = <&mmc1_sleep_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
};

&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins &eeprom_wp_pin>;

ov2659@30 {
compatible = "ti,ov2659";
reg = <0x30>;

port {
ov2659_1: endpoint {
remote-endpoint = <&vpfe0_ep>;
mclk-frequency = <12000000>;
};
};
};

cat24c256@50 {
compatible = "24c256";
reg = <0x50>;

pagesize = <64>;
};
};

&tscadc {
status = "okay";

adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};

&ecap0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
};

&epwmss0 {
status = "okay";
};

&dcan0 {
pinctrl-names = "default";
pinctrl-0 = <&dcan0_default>;
status = "okay";
};

&dcan1 {
pinctrl-names = "default";
pinctrl-0 = <&dcan1_default>;
status = "okay";
};

&mcasp1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
pinctrl-1 = <&mcasp1_sleep_pins>;

status = "okay";

op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0 0 1 2
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};

&elm {
status = "okay";
};

&gpmc {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <40>;
gpmc,cs-wr-off-ns = <40>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <25>;
gpmc,adv-wr-off-ns = <25>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <20>;
gpmc,oe-on-ns = <3>;
gpmc,oe-off-ns = <30>;
gpmc,access-ns = <30>;
gpmc,rd-cycle-ns = <40>;
gpmc,wr-cycle-ns = <40>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x00040000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00040000 0x00040000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00080000 0x00040000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x000C0000 0x00040000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00100000 0x00080000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x00180000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x00280000 0x00040000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x002C0000 0x00040000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00300000 0x00700000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00A00000 0x0F600000>;
};
};
};

&dss {
status = "ok";

pinctrl-names = "default", "sleep";
pinctrl-0 = <&dss_pinctrl_default>;
pinctrl-1 = <&dss_pinctrl_sleep>;
port {
dpi_out: endpoint@0 {
remote-endpoint = <&sii9022_in>;
data-lines = <24>;
};
};
};

&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};

&vpfe1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&vpfe1_pins_default>;
pinctrl-1 = <&vpfe1_pins_sleep>;

/* Camera port */
port {
vpfe1_ep: endpoint {
remote-endpoint = <&ov2659_0>;
if_type = <2>;
bus_width = <8>;
hdpol = <0>;
vdpol = <0>;
};
};
};

&vpfe0 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&vpfe0_pins_default>;
pinctrl-1 = <&vpfe0_pins_sleep>;

/* Camera port */
port {
vpfe0_ep: endpoint {
remote-endpoint = <&ov2659_1>;
if_type = <2>;
bus_width = <8>;
hdpol = <0>;
vdpol = <0>;
};
};
};

&clkout_32k_mux_ck {
clock-default = <&clk_32768_ck>;
};

&wkup_m3 {
ti,set-io-isolation;
};

Regard,

Pham Toan

Hi Yordan,

thanks you for your support.

I try to change dts file as below but no HDMI output. are there any misktakes in my dts file ?

/dts-v1/;

#include "am4372.dtsi"

#include <dt-bindings/pinctrl/am43xx.h>

#include <dt-bindings/pwm/pwm.h>

/ {

model = "MYIR Rico Board";

compatible = "myir,ricoboard","ti,am4372","ti,am43";

vmmcsd_fixed: fixedregulator-sd {

compatible = "regulator-fixed";

regulator-name = "vmmcsd_fixed";

regulator-min-microvolt = <3300000>;

regulator-max-microvolt = <3300000>;

enable-active-high;

};

evm_v3p3: tps63031 {

compatible = "regulator-fixed";

regulator-name = "evm_v3p3";

regulator-min-microvolt = <3300000>;

regulator-max-microvolt = <3300000>;

};

aliases {

display0 = &lcd0;

display1 = &hdmi0;

};

lcd0: display@0 {

compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";

video-source = <&dpi>;

data-lines = <24>;

panel-timing {

clock-frequency = <36000000>;

hactive = <800>;

vactive = <480>;

hfront-porch = <210>;

hback-porch = <1>;

hsync-len = <43>;

vback-porch = <1>;

vfront-porch = <22>;

vsync-len = <22>;

hsync-active = <0>;

vsync-active = <0>;

de-active = <1>;

pixelclk-active = <1>;

};

};

/* 4.3 inch, 480x272 resolution LCD, MYiR */

/* lcd0: display@0 {

compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";

video-source = <&dpi>;

data-lines = <24>;

panel-timing {

clock-frequency = <9600000>;

hactive = <480>;

vactive = <272>;

hfront-porch = <2>;

hback-porch = <2>;

hsync-len = <41>;

vback-porch = <2>;

vfront-porch = <2>;

vsync-len = <10>;

hsync-active = <0>;

vsync-active = <0>;

de-active = <1>;

pixelclk-active = <1>;

};

};

*/

/*

hdmi0: connector@1 {

compatible = "ti,hdmi_connector";

video-source = <&sii9022>;

};

*/

hdmi0: connector@1 {

compatible = "ti,hdmi_connector";

label = "hdmi";

type = "b";

port {

hdmi_connector_in: endpoint {

remote-endpoint = <&sii9022_out>;

};

};

};

sound {

compatible = "ti,da830-evm-audio";

ti,model = "AM437x-GP-EVM";

ti,audio-codec = <&tlv320aic3106>;

ti,mcasp-controller = <&mcasp1>;

ti,codec-clock-rate = <12000000>;

ti,audio-routing =

"Headphone Jack",       "HPLOUT",

"Headphone Jack",       "HPROUT",

"LINE1L",               "Line In",

"LINE1R",               "Line In";

};

/* Gpio keys, MYiR */

gpio_keys {

compatible = "gpio-keys";

#address-cells = <1>;

#size-cells = <0>;

user_key1 {

label = "user_key1";

gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>;

linux,code = <102>;

gpio-key,wakeup;

};

user_key2 {

label = "user_key2";

gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;

linux,code = <158>;

gpio-key,wakeup;

};

};

/* Gpio leds, MYiR */

gpio-leds {

compatible = "gpio-leds";

status_led0 {

label = "status_led0";

gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;

linux,default-trigger = "heartbeat";

};

status_led1 {

label = "status_led1";

gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;

default-state = "off";

};

status_led2 {

label = "status_led2";

gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;

default-state = "off";

};

status_led3 {

label = "status_led3";

gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;

default-state = "off";

};

};

backlight {

compatible = "pwm-backlight";

pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;

brightness-levels = <0 51 53 56 62 75 101 152 255>;

default-brightness-level = <1>;

};

cpus {

cpu@0 {

cpu0-supply = <&dcdc2>;

};

};

};

&am43xx_pinmux {

pinctrl-names = "default";

pinctrl-0 = <&clkout2_pin &ddr3_vtt_toggle_default>;

pinctrl-1 = <&clkout1_pin>;

i2c1_pins_default: i2c1_pins_default {

pinctrl-single,pins = <

0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */

0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */

>;

};

i2c1_pins_sleep: i2c1_pins_sleep {

pinctrl-single,pins = <

0x15c (PIN_INPUT_PULLUP | MUX_MODE7)

0x158 (PIN_INPUT_PULLUP | MUX_MODE7)

>;

};

cpsw_default: cpsw_default {

pinctrl-single,pins = <

/* Slave 1 */

0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */

0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */

0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */

0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */

0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */

0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */

0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */

0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */

0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */

0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */

0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */

0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */

>;

};

cpsw_sleep: cpsw_sleep {

pinctrl-single,pins = <

/* Slave 1 reset value */

0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)

>;

};

davinci_mdio_default: davinci_mdio_default {

pinctrl-single,pins = <

/* MDIO */

0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */

0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */

>;

};

davinci_mdio_sleep: davinci_mdio_sleep {

pinctrl-single,pins = <

/* MDIO reset value */

0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)

>;

};

mmc1_pins: pinmux_mmc1_pins {

pinctrl-single,pins = <

0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */

0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */

0x0f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */

0x0f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */

0x0f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */

0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */

0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */

>;

};

mmc1_sleep_pins: pinmux_mmc1_sleep_pins {

pinctrl-single,pins = <

0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */

0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */

0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */

0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */

0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */

0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */

>;

};

emmc_pins: pinmux_emmc_pins {

pinctrl-single,pins = <

0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */

0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */

0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */

0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */

0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */

0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */

0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */

0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */

0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */

0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */

>;

};

ddr3_vtt_toggle_default: ddr_vtt_toggle_default {

pinctrl-single,pins = <

0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */

>;

};

i2c0_pins: pinmux_i2c0_pins {

pinctrl-single,pins = <

0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_sda.i2c0_sda */

0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_scl.i2c0_scl */

>;

};

i2c1_pins: i2c1_pins {

pinctrl-single,pins = <

0x240   (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1)  /* i2c1_scl */

0x248   (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1)  /* i2c1_sda */

>;

};

dss_pinctrl_default: dss_pinctrl_default {

pinctrl-single,pins = <

0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */

0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)

0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)

0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)

0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)

0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)

0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)

0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */

0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */

0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)

0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */

0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */

0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */

0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */

0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */

0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* GPIO 5_8 to select LCD / HDMI */

>;

};

dss_pinctrl_sleep: dss_pinctrl_sleep {

pinctrl-single,pins = <

0x020 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)

0x024 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)

0x028 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)

0x02C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)

0x030 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)

0x034 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)

0x038 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)

0x03C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2)

0x0A0 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

0x0A4 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

0x0A8 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

0x0AC (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

0x0B0 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

0x0B4 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

0x0B8 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

0x0BC (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)

0x0C0 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)

0x0C4 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

0x0C8 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)

0x0CC (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)

0x0D0 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

0x0D4 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

0x0D8 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)

0x0DC (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)

0x0E0 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)

0x0E4 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)

0x0E8 (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

0x0EC (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | PULL_DISABLE | INPUT_EN | MUX_MODE7)

0x238 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)

>;

};

ecap0_pins: backlight_pins {

pinctrl-single,pins = <

0x164 0x0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */

>;

};

pixcir_ts_pins: pixcir_ts_pins {

pinctrl-single,pins = <

0x264 (PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */

>;

};

clkout2_pin: clkout2_pin {

pinctrl-single,pins = <

0x274 (PIN_OUTPUT_PULLUP | MUX_MODE3)

>;

};

clkout1_pin: clkout1_pin {

pinctrl-single,pins = <

0x270 (PIN_OUTPUT_PULLUP | MUX_MODE3)

>;

};

dcan0_default: dcan0_default_pins {

pinctrl-single,pins = <

0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_ctsn.d_can0_tx */

0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */

>;

};

dcan1_default: dcan1_default_pins {

pinctrl-single,pins = <

0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.d_can1_tx */

0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */

>;

};

mcasp1_pins: mcasp1_pins {

pinctrl-single,pins = <

0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */

0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */

0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */

0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */

>;

};

mcasp1_sleep_pins: mcasp1_sleep_pins {

pinctrl-single,pins = <

0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)

0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)

>;

};

nand_flash_x8: nand_flash_x8 {

pinctrl-single,pins = <

0x26C(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */

0x0  (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */

0x4  (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */

0x8  (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */

0xc  (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */

0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */

0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */

0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */

0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */

0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */

0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */

0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0  */

0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */

0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */

0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */

0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */

>;

};

uart0_pins: uart0_pins {

pinctrl-single,pins = <

0x170 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */

0x174 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */

>;

};

tsl2550: tsl2550@39 {

compatible = "taos,tsl2550";

reg = <0x39>;

};

tmp275: tmp275@48 {

compatible = "ti,tmp275";

reg = <0x48>;

};

vpfe0_pins_default: vpfe0_pins_default {

pinctrl-single,pins = <

/*0x270 (PIN_OUTPUT_PULLUP | MUX_MODE3) */  /* xdma_event_intr0.clkout1 mode 3*/

0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/

0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/

0x1B8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_field mode 0*/

0x1BC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_wen mode 0*/

0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/

0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/

0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/

0x208 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/

0x20C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/

0x210 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/

0x214 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/

0x218 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/

0x21C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/

0x220 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/

0x224 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/

>;

};

vpfe0_pins_sleep: vpfe0_pins_sleep {

pinctrl-single,pins = <

0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/

0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/

0x1B8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_field mode 0*/

0x1BC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_wen mode 0*/

0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/

0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/

0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/

0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/

0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/

0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/

0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/

0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/

0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/

0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/

0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/

>;

};

vpfe1_pins_default: vpfe1_pins_default {

pinctrl-single,pins = <

/* 0x270 (PIN_OUTPUT_PULLUP | MUX_MODE3) */ /* xdma_event_intr0.clkout1 mode 3*/

0x1CC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/

0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/

0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/

0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/

0x1DC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/

0x1E0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_field mode 0*/

0x1E4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_wen mode 0*/

0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/

0x1EC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/

0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/

0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/

0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/

0x1FC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/

0x200 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/

0x204 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/

>;

};

vpfe1_pins_sleep: vpfe1_pins_sleep {

pinctrl-single,pins = <

0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/

0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/

0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/

0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/

0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/

0x1E0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_field mode 0*/

0x1E4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_wen mode 0*/

0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/

0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/

0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/

0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/

0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/

0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/

0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/

0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/

>;

};

/* Qspi, MYiR */

qspi1_default: qspi1_default {

pinctrl-single,pins = <

0x7c (PIN_INPUT_PULLUP | MUX_MODE3)

0x88 (PIN_INPUT_PULLUP | MUX_MODE2)

0x90 (PIN_INPUT_PULLUP | MUX_MODE3)

0x94 (PIN_INPUT_PULLUP | MUX_MODE3)

0x98 (PIN_INPUT_PULLUP | MUX_MODE3)

0x9c (PIN_INPUT_PULLUP | MUX_MODE3)

>;

};

/* eeprom, MYiR */

eeprom_wp_pin: eeprom_wp_pin {

pinctrl-single,pins = <

0x2a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)

>;

};

};

&i2c0 {

       status = "okay";

       pinctrl-names = "default";

       pinctrl-0 = <&i2c0_pins>;

clock-frequency = <100000>;

/* Set OPP50 (0.95V) for VDD MPU and core */

sleep-sequence = /bits/ 8 <

0x02 0x24 0x10 0x6b /* Password unlock 1 */

0x02 0x24 0x16 0x8A /* Set DCDC1 (Core) to 0.95V */

0x02 0x24 0x10 0x67 /* Password unlock 3 */

0x02 0x24 0x1A 0x86 /* Apply DCDC changes */

>;

/* Set OPP100 (1.10V) for VDD core */

wake-sequence = /bits/ 8 <

0x02 0x24 0x10 0x6B /* Password unlock 2 */

0x02 0x24 0x16 0x99 /* Set DCDC1 (Core) to 1.1V */

0x02 0x24 0x10 0x67 /* Password unlock 3 */

0x02 0x24 0x1A 0x86 /* Apply DCDC changes */

>;

tps65218: tps65218@24 {

reg = <0x24>;

compatible = "ti,tps65218";

interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */

interrupt-parent = <&gic>;

interrupt-controller;

#interrupt-cells = <2>;

dcdc1: regulator-dcdc1 {

compatible = "ti,tps65218-dcdc1";

/* VDD_CORE voltage limits min of OPP50 and max of OPP100 */

regulator-name = "vdd_core";

regulator-min-microvolt = <912000>;

regulator-max-microvolt = <1144000>;

regulator-boot-on;

regulator-always-on;

};

dcdc2: regulator-dcdc2 {

compatible = "ti,tps65218-dcdc2";

/* VDD_MPU voltage limits min of OPP50 and max of OPP_NITRO */

regulator-name = "vdd_mpu";

regulator-min-microvolt = <912000>;

regulator-max-microvolt = <1378000>;

regulator-boot-on;

regulator-always-on;

};

dcdc3: regulator-dcdc3 {

compatible = "ti,tps65218-dcdc3";

};

ldo1: regulator-ldo1 {

compatible = "ti,tps65218-ldo1";

regulator-min-microvolt = <1800000>;

regulator-max-microvolt = <1800000>;

regulator-boot-on;

regulator-always-on;

};

/* MYIR, for usb vbus control */

ls2: regulator-ls2 {

compatible = "ti,tps65218-ls2";

regulator-name = "vdd_vbus0";

};

ls3: regulator-ls3 {

compatible = "ti,tps65218-ls3";

regulator-name = "vdd_vbus1";

regulator-boot-on;

};

};

};

&i2c1 {

status = "okay";

pinctrl-names = "default", "sleep";

pinctrl-0 = <&i2c1_pins_default>;

pinctrl-1 = <&i2c1_pins_sleep>;

sii9022: sii9022@3b {

#sound-dai-cells = <0>;

compatible = "sil,sii9022";

reg = <0x3b>;

/*

i2s-fifo-routing = <

(ENABLE_BIT|CONNECT_SD0)

0

0

0

>;

*/

};

tlv320aic3106: tlv320aic3106@1b {

compatible = "ti,tlv320aic3106";

reg = <0x1b>;

status = "okay";

/* Regulators */

AVDD-supply = <&evm_v3p3>;

IOVDD-supply = <&evm_v3p3>;

DRVDD-supply = <&evm_v3p3>;

DVDD-supply = <&ldo1>;

};

ov2659@30 {

compatible = "ti,ov2659";

reg = <0x30>;

port {

ov2659_0: endpoint {

remote-endpoint = <&vpfe1_ep>;

mclk-frequency = <12000000>;

};

};

};

ports {

#address-cells = <1>;

#size-cells = <0>;

port@0 {

reg = <0>;

sii9022_in: endpoint {

remote-endpoint = <&dpi_out>;

};

};

port@1 {

reg = <1>;

sii9022_out: endpoint {

remote-endpoint = <&hdmi_connector_in>;

};

};

};

};

&rtc {

status = "okay";

};

&gpio0 {

status = "okay";

};

/* Added by MYiR for GPIO1 & GPIO2 */

&gpio1 {

status = "okay";

};

&gpio2 {

status = "okay";

};

&gpio3 {

status = "okay";

};

&gpio4 {

status = "okay";

};

&gpio5 {

status = "okay";

ti,no-reset;

};

/* Enable qspi, 16MB S25FL128S norflash, MYiR */

&qspi {

status = "okay";

pinctrl-names = "default";

pinctrl-0 = <&qspi1_default>;

qspi-gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;

spi-max-frequency = <24000000>;

m25p80@0 {

compatible = "s25fl128s";

spi-max-frequency = <24000000>;

reg = <0>;

spi-cpol;

spi-cpha;

spi-tx-bus-width = <1>;

spi-rx-bus-width = <4>;

#address-cells = <1>;

#size-cells = <1>;

/* MTD partition table.

* The ROM checks the first 512KiB

* for a valid file to boot(XIP).

*/

partition@0 {

label = "QSPI.U_BOOT";

reg = <0x00000000 0x000080000>;

};

partition@1 {

label = "QSPI.U_BOOT.backup";

reg = <0x00080000 0x00080000>;

};

partition@2 {

label = "QSPI.U_BOOT_ENV";

reg = <0x00100000 0x00020000>;

};

partition@3 {

label = "QSPI.U-BOOT-ENV.backup";

reg = <0x00120000 0x00020000>;

};

partition@4 {

label = "QSPI.U-BOOT-DEVICETREE";

reg = <0x00140000 0x00010000>;

};

partition@5 {

label = "QSPI.KERNEL";

reg = <0x00150000 0x0500000>;

};

partition@6 {

label = "QSPI.FILESYSTEM";

reg = <0x00650000 0x9B0000>;

};

};

};

&dpi {

pinctrl-names = "default", "sleep";

pinctrl-0 = <&dss_pinctrl_default>;

pinctrl-1 = <&dss_pinctrl_sleep>;

};

&mac {

slaves = <1>;

pinctrl-names = "default", "sleep";

pinctrl-0 = <&cpsw_default>;

pinctrl-1 = <&cpsw_sleep>;

status = "okay";

};

&davinci_mdio {

pinctrl-names = "default", "sleep";

pinctrl-0 = <&davinci_mdio_default>;

pinctrl-1 = <&davinci_mdio_sleep>;

status = "okay";

};

&cpsw_emac0 {

phy_id = <&davinci_mdio>, <0>;

phy-mode = "rgmii";

};

&mmc2 {

vmmc-supply = <&vmmcsd_fixed>;

bus-width = <8>;

ti,non-removable;

pinctrl-names = "default";

pinctrl-0 = <&emmc_pins>;

status = "okay";

};

&mmc1 {

status = "okay";

vmmc-supply = <&vmmcsd_fixed>;

bus-width = <4>;

pinctrl-names = "default", "sleep";

pinctrl-0 = <&mmc1_pins>;

pinctrl-1 = <&mmc1_sleep_pins>;

cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;

};

&i2c0 {

status = "okay";

      pinctrl-names = "default";

       pinctrl-0 = <&i2c0_pins &eeprom_wp_pin>;

       ov2659@30 {

compatible = "ti,ov2659";

reg = <0x30>;

port {

ov2659_1: endpoint {

remote-endpoint = <&vpfe0_ep>;

mclk-frequency = <12000000>;

};

};

};

cat24c256@50 {

compatible = "24c256";

reg = <0x50>;

pagesize = <64>;

};

};

&tscadc {

status = "okay";

adc {

ti,adc-channels = <0 1 2 3 4 5 6 7>;

};

};

&ecap0 {

status = "okay";

pinctrl-names = "default";

pinctrl-0 = <&ecap0_pins>;

};

&epwmss0 {

status = "okay";

};

&dcan0 {

pinctrl-names = "default";

pinctrl-0 = <&dcan0_default>;

status = "okay";

};

&dcan1 {

pinctrl-names = "default";

pinctrl-0 = <&dcan1_default>;

status = "okay";

};

&mcasp1 {

pinctrl-names = "default", "sleep";

pinctrl-0 = <&mcasp1_pins>;

pinctrl-1 = <&mcasp1_sleep_pins>;

status = "okay";

op-mode = <0>; /* MCASP_IIS_MODE */

tdm-slots = <2>;

/* 4 serializers */

serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */

0 0 1 2

>;

tx-num-evt = <32>;

rx-num-evt = <32>;

};

&elm {

status = "okay";

};

&gpmc {

status = "disabled";

pinctrl-names = "default";

pinctrl-0 = <&nand_flash_x8>;

ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */

nand@0,0 {

reg = <0 0 0>; /* CS0, offset 0 */

nand-bus-width = <8>;

gpmc,device-width = <1>;

gpmc,sync-clk-ps = <0>;

gpmc,cs-on-ns = <0>;

gpmc,cs-rd-off-ns = <40>;

gpmc,cs-wr-off-ns = <40>;

gpmc,adv-on-ns = <0>;

gpmc,adv-rd-off-ns = <25>;

gpmc,adv-wr-off-ns = <25>;

gpmc,we-on-ns = <0>;

gpmc,we-off-ns = <20>;

gpmc,oe-on-ns = <3>;

gpmc,oe-off-ns = <30>;

gpmc,access-ns = <30>;

gpmc,rd-cycle-ns = <40>;

gpmc,wr-cycle-ns = <40>;

gpmc,wait-on-read = "true";

gpmc,wait-on-write = "true";

gpmc,bus-turnaround-ns = <0>;

gpmc,cycle2cycle-delay-ns = <0>;

gpmc,clk-activation-ns = <0>;

gpmc,wait-monitoring-ns = <0>;

gpmc,wr-access-ns = <40>;

gpmc,wr-data-mux-bus-ns = <0>;

ti,nand-ecc-opt = "bch16";

ti,elm-id = <&elm>;

/* MTD partition table */

/* All SPL-* partitions are sized to minimal length

* which can be independently programmable. For

* NAND flash this is equal to size of erase-block */

#address-cells = <1>;

#size-cells = <1>;

partition@0 {

label = "NAND.SPL";

reg = <0x00000000 0x00040000>;

};

partition@1 {

label = "NAND.SPL.backup1";

reg = <0x00040000 0x00040000>;

};

partition@2 {

label = "NAND.SPL.backup2";

reg = <0x00080000 0x00040000>;

};

partition@3 {

label = "NAND.SPL.backup3";

reg = <0x000C0000 0x00040000>;

};

partition@4 {

label = "NAND.u-boot-spl-os";

reg = <0x00100000 0x00080000>;

};

partition@5 {

label = "NAND.u-boot";

reg = <0x00180000 0x00100000>;

};

partition@6 {

label = "NAND.u-boot-env";

reg = <0x00280000 0x00040000>;

};

partition@7 {

label = "NAND.u-boot-env.backup1";

reg = <0x002C0000 0x00040000>;

};

partition@8 {

label = "NAND.kernel";

reg = <0x00300000 0x00700000>;

};

partition@9 {

label = "NAND.file-system";

reg = <0x00A00000 0x0F600000>;

};

};

};

&dss {

status = "ok";

pinctrl-names = "default", "sleep";

pinctrl-0 = <&dss_pinctrl_default>;

pinctrl-1 = <&dss_pinctrl_sleep>;

port {

dpi_out: endpoint@0 {

remote-endpoint = <&sii9022_in>;

data-lines = <24>;

};

};

};

&uart0 {

status = "okay";

pinctrl-names = "default";

pinctrl-0 = <&uart0_pins>;

};

&vpfe1 {

status = "okay";

pinctrl-names = "default", "sleep";

pinctrl-0 = <&vpfe1_pins_default>;

pinctrl-1 = <&vpfe1_pins_sleep>;

/* Camera port */

port {

vpfe1_ep: endpoint {

remote-endpoint = <&ov2659_0>;

if_type = <2>;

bus_width = <8>;

hdpol = <0>;

vdpol = <0>;

};

};

};

&vpfe0 {

status = "okay";

pinctrl-names = "default", "sleep";

pinctrl-0 = <&vpfe0_pins_default>;

pinctrl-1 = <&vpfe0_pins_sleep>;

/* Camera port */

port {

vpfe0_ep: endpoint {

remote-endpoint = <&ov2659_1>;

if_type = <2>;

bus_width = <8>;

hdpol = <0>;

vdpol = <0>;

};

};

};

&clkout_32k_mux_ck {

clock-default = <&clk_32768_ck>;

};

&wkup_m3 {

ti,set-io-isolation;

};

thanks you very much

Regard,

Pham Toan

Hi,

I noticed you've missed the lcd_pins: lcd_pins and &gpio5 dts node. GPIO5_8 is used to select LCD or HDMI in your setup. 
So to summarize you should have the following display related nodes in your dts file: 

 #include <dt-bindings/sound/sii9022-audio.h>

hdmi: connector {
              compatible = "hdmi-connector";
              label = "hdmi";

              type = "b";

             port {
                       hdmi_connector_in: endpoint {
                                    remote-endpoint = <&sii9022_out>;
                       };
             };
};

sound@1 {
           compatible = "simple-audio-card";
           simple-audio-card,name = "HDMI";
           simple-audio-card,format = "i2s";
           simple-audio-card,bitclock-master = <&hdmi_dailink_master>;
           simple-audio-card,frame-master = <&hdmi_dailink_master>;
           hdmi_dailink_master: simple-audio-card,cpu {
                       sound-dai = <&mcasp1>;
                       system-clock-frequency = <24000000>;
                       system-clock-direction = "out";
          };

          simple-audio-card,codec {
                      sound-dai = <&sii9022>;
                      system-clock-frequency = <12000000>;
          };
 };

&lcd_bl {
         status = "disabled";
};

&sound0 {
          status = "disabled";
};

&i2c1 {
           sii9022: sii9022@3b {
                    #sound-dai-cells = <0>;
                    compatible = "sil,sii9022";
                    reg = <0x3b>;

                     i2s-fifo-routing = <
                                     (ENABLE_BIT|CONNECT_SD0)
                                      0
                                      0
                                      0
                     >;

                    /* XXX 'SelLCDorHDMI' Gpio, LOW to select HDMI */
                    reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;

                    ports {
                             #address-cells = <1>;
                             #size-cells = <0>;

                              port@0 {
                                           reg = <0>;

                                           sii9022_in: endpoint {
                                                      remote-endpoint = <&dpi_out>;
                                            };
                              };

                             port@1 {
                                            reg = <1>;

                                            sii9022_out: endpoint {
                                                      remote-endpoint = <&hdmi_connector_in>;
                                            };
                             };
                   };
         };
};

&dss {
                port {
                           dpi_out: endpoint@0 {
                                   remote-endpoint = <&sii9022_in>;
                                   data-lines = <24>;
                           };
                 };
};

lcd_bl: backlight {
              compatible = "pwm-backlight";
              pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
              brightness-levels = <0 51 53 56 62 75 101 152 255>;
              default-brightness-level = <8>;
};

lcd0: display {
                 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
                 label = "lcd";

                 panel-timing {
                                clock-frequency = <33000000>;
                                 hactive = <800>;
                                 vactive = <480>;
                                  hfront-porch = <210>;
                                  hback-porch = <16>;
                                 hsync-len = <30>;
                                 vback-porch = <10>;
                                 vfront-porch = <22>;
                                 vsync-len = <13>;
                                 hsync-active = <0>;
                                 vsync-active = <0>;
                                 de-active = <1>;
                                 pixelclk-active = <1>;
                  };

                 port {
                            lcd_in: endpoint {
                                   remote-endpoint = <&dpi_out>;
                            };
                 };
};

&am43xx_pinmux {  

           ........................

           dss_pinctrl_default: dss_pinctrl_default {
                              pinctrl-single,pins = <
                                        0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
                                        0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
                                        0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
                                        0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
                                        0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
                                        0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
                                        0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
                                        0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
                                        0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
                                        0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
                                        0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
                                        0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
                                        0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
                                        0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
                                         0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */

                            >;
       };

       dss_pinctrl_sleep: dss_pinctrl_sleep {
                           pinctrl-single,pins = <
                                              0x020 (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x024 (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x028 (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x02C (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x030 (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x034 (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x038 (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x03C (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x0A0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | PULL_DISABLE | MUX_MODE7)
                                              0x0A4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | PULL_DISABLE | MUX_MODE7)
                                              0x0A8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | PULL_DISABLE | MUX_MODE7)
                                              0x0AC (DS0_PULL_UP_DOWN_EN | INPUT_EN | PULL_DISABLE | MUX_MODE7)
                                              0x0B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | PULL_DISABLE | MUX_MODE7)
                                              0x0B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | PULL_DISABLE | MUX_MODE7)
                                              0x0B8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | PULL_DISABLE | MUX_MODE7)
                                              0x0BC (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x0C0 (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x0C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | PULL_DISABLE | MUX_MODE7)
                                              0x0C8 (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x0CC (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x0D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | PULL_DISABLE | MUX_MODE7)
                                              0x0D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | PULL_DISABLE | MUX_MODE7)
                                              0x0D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | PULL_DISABLE | MUX_MODE7)
                                              0x0DC (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x0E0 (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x0E4 (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                              0x0E8 (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                                             0x0EC (DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
                              >;
                 };

                 lcd_pins: lcd_pins {
                                               pinctrl-single,pins = <
                                                          /* GPIO 5_8 to select LCD / HDMI */
                                                         0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
                                                >;
                };

               .........................................................

};

&gpio5 {
              status = "okay";
              ti,no-reset-on-init;
};

Hope this helps. 

Best Regards, 

Yordan

Dear,

I show my schematic. I saw that my schematic dont have GPIO5_8 is used to select LCD or HDMI.

thanks you very much

Pham Toan,