• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 102 subscribers
  • Views 1861 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Limits of EtherCAT DC minimum cycle

schezow
Prodigy 180 points
Other Parts Discussed in Thread: AM3359

Hi~

I'm using the AM3359 ICE v2 + SDK 1.1.0.8 + Intel e1000e NIC + IgH EtherCAT master v1.5.2 and I have been testing  a DC cycle in 100us sampling time. 

Using the IgH DC example code, the master and slaves well operated(no errors, no warnings).

I found that the IgH EtherCAT supports DC Sync1 mode. So, I checked DC related objects (0x1c32 registers).

0x1c32:02 (cycle time) : In my case 100,000(100us) ~ 500,000(500us)

0x1c32:05 (Min Cycle Time) : 31,200 (31.2us)

0x1c32:06 (Calc + Copy Time) : 0

0x1c32:09 (Delay Time) : 0

I think that the cycle time is possible in a range of 32us ~ 100us.

In the real test, however, DC example code with under 100us sampling time was not working. Datagram skipped message occurred.

And in the E2E community article, Frank said ICE's maximum freq is 10kHz(100us). 

What is the problem? ICE hardware or SDK's restriction? if not, IgH EtherCAT master's software problem?

Regards.

  • 0
    TI__Guru**** 393215 points
    Hi,

    I will forward this to the ISDK team.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 180 points

    To Biser Gatchev.

    I confused datagram skipped message with synchronization error.

    In the rane of 50~100us sampling time, the system log messages are following

    Please forward this article too.

    Regards.

  • 0 in reply to schezow
    TI__Mastermind 42550 points
    Hi,
    To do < 100us, heavy optimizations are required in slave application, make sure that I/Os are done using fast interface - current example uses I2C for digital out and McSPI for digital input...
    Synchronization error may be due to non-real time master - are you using RT kernel ? Did you profile latency (this is off topic already :) )?
    This can also be due Rx PDO toggle failure counter exceeding max limit : infosys.beckhoff.com/english.php;id=8756
  • 0 in reply to PratheeshGangadhar
    Prodigy 180 points

    To Pratheesh.

    1. Slave Application

    I have used SDK EtherCAT Application example(ecat_appl). No edit and no change.

    How can I optimize this example? I think this application code is very simple.

    2. Kernel Patch

    I have patched RT kernel already. Ubuntu 12.04 with the kernel version is 3.2.0-RT10

    3. Other Latency.

    In the range of upper 100us (includes 100us), the program output is only AL states : 0x08 (OP state)

    And system log messages (dmesg) are following:

    Except Warning 0-0 message (aka this is IgH's problem), there are no warnings or no sync errors.

    I want to know where part of ethercat system optimize DC sync to do < 100us?

    and is it possible to optimize that part?