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Pin muxing for an ether net chip KSZ8081RNA

Other Parts Discussed in Thread: AM3352

Hi Forum,

I wonder if any one can shed light on my PIN MUXING PROCESS for BB compatible custom board using AM3352 CPU and MICREL KSZ8081RNA chip set for an ether net. The data sheet from Micrel strongly advise to use 25Mhz clock frequency; which available on board of the chip under external-ref.

The extract from board/ti/am335x/mux.c

 static struct module_pin_mux rmii1_pin_mux[] = {

{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* GWCS1X_RMII_1 -> rmii1_crs_dv -> H17 */
{OFFSET(mii1_txen), MODE(1)}, /* GWCS1X_RMII_1 -> rmii1_txen -> J16 */
{OFFSET(mii1_txd0), MODE(1)}, /* GWCS1X_RMII_1 -> rmii1_txd0 -> K17 */
{OFFSET(mii1_txd1), MODE(1) | RXACTIVE}, /* GWCS1X_RMII_1 -> rmii1_txd1 -> K16 */
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* GWCS1X_RMII_1 -> rmii1_rxd0 -> M16 */
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* GWCS1X_RMII_1 -> rmii1_rxd1 -> L15 */
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* GWCS1X_RMII_1 -> rmii1_refclk -> H18 (Pg37dsheet 0=25Mhz,1=50Mhz) */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* GWCS1X_MDIO 1 -> mdio_data -> M17 */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* GWCS1X_MDIO 1 -> mdio_clk -> M18 */
{-1}
};
/* Initialisaton for the second ethernet port on the board */
static struct module_pin_mux rmii2_pin_mux[] = {
{OFFSET(mii1_crs), MODE(2) | RXACTIVE}, /* GWCS1X_RMII_2 -> rmii2_crs_dv -> T17 */
{OFFSET(mii1_txen), MODE(3)}, /* GWCS1X_RMII_2 -> rmii2_txen -> R13 */
{OFFSET(mii1_txd0), MODE(3)}, /* GWCS1X_RMII_2 -> rmii2_txd0 -> V15 */
{OFFSET(mii1_txd1), MODE(3) | RXACTIVE}, /* GWCS1X_RMII_2 -> rmii2_txd0 -> R14 */
{OFFSET(mii1_rxd0), MODE(3) | RXACTIVE}, /* GWCS1X_RMII_2 -> rmii2_rxd0 -> V17 */
{OFFSET(mii1_rxd1), MODE(3) | RXACTIVE}, /* GWCS1X_RMII_2 -> rmii2_rxd1 -> T16 */
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* GWCS1X_RMII_2 -> rmii2_refclk -> H16 (Pg37dsheet 0=25mhz 1=50Mhz) */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* GWCS1X_MDIO 1 -> mdio_data -> M17 */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* GWCS1X_MDIO 1 -> mdio_clk -> M18 */
{-1},
};


configure_module_pin_mux(i2c1_pin_mux);

configure_module_pin_mux(rmii1_pin_mux);

configure_module_pin_mux(rmii2_pin_mux);

configure_module_pin_mux(mmc0_pin_mux);

/* We do not have second mmc slot */
// configure_module_pin_mux(mmc1_pin_mux);

  • Imran Khan14 said:

    The data sheet from Micrel strongly advise to use 25Mhz clock frequency; which available on board of the chip under external-ref.

    What do you mean by this? Are you attempting to use an AM3352-derived clock for your PHY?

  • For the MICREL ksz8081 chips has on board reference clock which oscillating under two different freq. 25Mhz and 50Mhz.
    Hence, therefore we are using onboard clock freq. As Micrel advise to use 25Mhz as initial for the both chips (Phy)
    You may noticed the statement ....
    Phy or chip 1
    {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* GWCS1X_RMII_2 -> rmii2_refclk -> H16 (Pg37dsheet 0=25mhz 1=50Mhz) */
    Phy or chip 2
    {OFFSET(rmii1_refclk), MODE(1) | RXACTIVE}, /* GWCS1X_RMII_2 -> rmii2_refclk -> H16 (Pg37dsheet 0=25mhz 1=50Mhz) */

    PS: previous post please ignore the setting for 2 chip or phy.