am335x set gpio mode

Ahn

Intellectual 1000 points

hi,

I'm read the http://processors.wiki.ti.com/index.php/Linux_PSP_GPIO_Driver_Guide.

I want to set the gpio1_28, gpio1_30 and gpio1_31 as a gpio_mode( for button event control ).

But, button event is not occured. ( When using the gpio1_27, button event is occurred. )

How do I set up the device tree?

Here is my code :

err = gpio_request(param->pio, name);

err = gpio_direction_input(param->pio);

irq_num = gpio_to_irq(param->pio);

err = request_irq(irq_num, gpio_event_handler, 0, name, (void*)(param->pio));

err = irq_set_irq_type(irq_num, IRQ_TYPE_EDGE_RISING);

gpio_export(param->pio, true);

Here is my environment :

u-boot-2014.07-g7e537bf

linux-3.14.26-g2489c02

without emmc

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Hi,

I will forward this to the SW team.

0 Kemal R. Shakir over 8 years ago in reply to Biser Gatchev-XID

TI__Guru 55345 points

Hello Ahn,

First check your dts file and find out if these pin-outs are not in use by another peripheral. You can refer to kernel Documentation/devicetree/bindings/gpio/gpio.txt and Pin Mux-Tool auto-generated dts file to setup your device tree.

Best regards,
Kemal

0 Ahn over 8 years ago in reply to Kemal R. Shakir

Intellectual 1000 points

Hi,

The am335x-boneblack.dts amended as follows.

And another dtsi files were not modified.

Please check my device tree.

###########################################################################

/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;

#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"

&ldo3_reg {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};

&am33xx_pinmux {
mcasp0_pins: mcasp0_pins {
pinctrl-single,pins = <
0x1ac (PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */
0x190 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
0x194 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
>;
};

mcasp0_pins_sleep: mcasp0_pins_sleep {
pinctrl-single,pins = <
0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.mcasp0_ahclkx */
0x190 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_aclkx.mcasp0_aclkx */
0x194 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsx.mcasp0_fsx */
0x198 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr0.mcasp0_axr0 */
>;
};

spi0_pins: spi0_pins {
pinctrl-single,pins = <
0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
0x158 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
>;
};

nandflash_pins_default: nandflash_pins_default {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};

nandflash_pins_sleep: nandflash_pins_sleep {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};

uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
0x180 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (D16) uart1_rxd.uart1_rxd */
0x184 ( PIN_OUTPUT_PULLUP | MUX_MODE0 ) /* (D15) uart1_txd.uart1_txd */
0x178 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (D18) uart1_ctsn.uart1_ctsn */
0x17c ( PIN_OUTPUT_PULLUP | MUX_MODE0 ) /* (D17) uart1_rtsn.uart1_rtsn */
0xf0 ( PIN_INPUT_PULLUP | MUX_MODE4 ) /* (F17) mmc0_dat3.uart1_dcdn */
0xf4 ( PIN_INPUT_PULLUP | MUX_MODE4 ) /* (F18) mmc0_dat2.uart1_dsrn */
0xf8 ( PIN_OUTPUT_PULLUP | MUX_MODE4 ) /* (G15) mmc0_dat1.uart1_dtrn */
0xfc ( PIN_INPUT_PULLUP | MUX_MODE4 ) /* (G16) mmc0_dat0.uart1_rin */
>;
};

uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
0x160 ( PIN_INPUT_PULLUP | MUX_MODE1 ) /* (C15) spi0_cs1.uart3_rxd */
0x164 ( PIN_OUTPUT_PULLUP | MUX_MODE1 ) /* (C18) eCAP0_in_PWM0_out.uart3_txd */
0x100 ( PIN_INPUT_PULLUP | MUX_MODE2 ) /* (G17) mmc0_clk.uart3_ctsn */
0x104 ( PIN_OUTPUT_PULLUP | MUX_MODE2 ) /* (G18) mmc0_cmd.uart3_rtsn */
>;
};
};

&mcasp0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp0_pins>;
pinctrl-1 = <&mcasp0_pins_sleep>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 0 0 0
>;
tx-num-evt = <1>;
rx-num-evt = <1>;
};

&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
m25p80@0 {
compatible = "spansion,s25fl132k";
spi-max-frequency = <48000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "mlo";
reg = <0x00000000 0x00020000>;
};
partition@1 {
label = "uboot";
reg = <0x00020000 0x000a0000>;
};
partition@2 {
label = "env";
reg = <0x000c0000 0x00010000>;
};
partition@3 {
label = "macadr";
reg = <0x000d0000 0x00010000>;
};
partition@4 {
label = "header_info";
reg = <0x000e0000 0x00010000>;
};
partition@5 {
label = "spare1";
reg = <0x000f0000 0x00010000>;
};
partition@6 {
label = "upgrade_info";
reg = <0x00100000 0x00010000>;
};
partition@7 {
label = "splash";
reg = <0x00110000 0x00020000>;
};
partition@8 {
label = "spare2";
reg = <0x00130000 0x00250000>;
};
partition@9 {
label = "database";
reg = <0x00380000 0x00080000>;
};
};
};

&elm {
status = "okay";
};

&gpmc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nandflash_pins_default>;
pinctrl-1 = <&nandflash_pins_sleep>;
status = "okay";
ranges = <0 0 0x08000000 0x10000000>;
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x00000000 0x06000000>;
};
partition@1 {
label = "kernel2";
reg = <0x06000000 0x06000000>;
};
partition@2 {
label = "misc";
reg = <0x0c000000 0x04000000>;
};
};
};

&mmc1 {
status = "disabled";
};

&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;

status = "okay";
};

&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;

status = "okay";
};

/ {
cs4344: cs4344@0 {
compatible = "ti,cs4344";
};

sound {
compatible = "ti,cs4344-evm-audio";
ti,model = "CS4344";
ti,audio-codec = <&cs4344>;
ti,mcasp-controller = <&mcasp0>;
ti,codec-clock-rate = <12000000>;
};
};

###########################################################################

0 Kemal R. Shakir over 8 years ago in reply to Ahn

TI__Guru 55345 points

Check the included "am335x-bone-common.dtsi" here the gpio1_30 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ and gpio1_31 0x84 ( PIN_INPUT | MUX_MODE7 ) /* (V9) gpmc_csn2.gpio1[31] */ are in mux mode 2 which are mmc1_clk and mmc1_cmd. Could you attach the output of this command cat /sys/kernel/debug/pinctrl/44e10800.pinmux/pinmux-pins

0 Ahn over 8 years ago in reply to Kemal R. Shakir

Intellectual 1000 points

Hi,

It was disable the mmc in the kernel config.

- # CONFIG_MMC is not set

And device tree.

&mmc1 {
status = "disabled";
};

# cat /sys/kernel/debug/pinctrl/44e10800.pinmux/pinmux-pins
Pinmux settings per pin
Format: pin (name): mux_owner gpio_owner hog?
pin 0 (44e10800.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 1 (44e10804.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 2 (44e10808.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 3 (44e1080c.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 4 (44e10810.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 5 (44e10814.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 6 (44e10818.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 7 (44e1081c.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 8 (44e10820.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 9 (44e10824.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 10 (44e10828.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 11 (44e1082c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 12 (44e10830.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 13 (44e10834.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 14 (44e10838.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 15 (44e1083c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 16 (44e10840.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 17 (44e10844.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 18 (44e10848.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 19 (44e1084c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 20 (44e10850.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 21 (44e10854.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 22 (44e10858.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 23 (44e1085c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 24 (44e10860.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 25 (44e10864.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 26 (44e10868.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 27 (44e1086c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 28 (44e10870.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 29 (44e10874.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 30 (44e10878.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 31 (44e1087c.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 32 (44e10880.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 33 (44e10884.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 34 (44e10888.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 35 (44e1088c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 36 (44e10890.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 37 (44e10894.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 38 (44e10898.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 39 (44e1089c.0): 50000000.gpmc (GPIO UNCLAIMED) function nandflash_pins_default group nandflash_pins_default
pin 40 (44e108a0.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 41 (44e108a4.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 42 (44e108a8.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 43 (44e108ac.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 44 (44e108b0.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 45 (44e108b4.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 46 (44e108b8.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 47 (44e108bc.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 48 (44e108c0.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 49 (44e108c4.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 50 (44e108c8.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 51 (44e108cc.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 52 (44e108d0.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 53 (44e108d4.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 54 (44e108d8.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 55 (44e108dc.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 56 (44e108e0.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 57 (44e108e4.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 58 (44e108e8.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 59 (44e108ec.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 60 (44e108f0.0): 48022000.serial (GPIO UNCLAIMED) function pinmux_uart1_pins group pinmux_uart1_pins
pin 61 (44e108f4.0): 48022000.serial (GPIO UNCLAIMED) function pinmux_uart1_pins group pinmux_uart1_pins
pin 62 (44e108f8.0): 48022000.serial (GPIO UNCLAIMED) function pinmux_uart1_pins group pinmux_uart1_pins
pin 63 (44e108fc.0): 48022000.serial (GPIO UNCLAIMED) function pinmux_uart1_pins group pinmux_uart1_pins
pin 64 (44e10900.0): 481a6000.serial (GPIO UNCLAIMED) function pinmux_uart3_pins group pinmux_uart3_pins
pin 65 (44e10904.0): 481a6000.serial (GPIO UNCLAIMED) function pinmux_uart3_pins group pinmux_uart3_pins
pin 66 (44e10908.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 67 (44e1090c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 68 (44e10910.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 69 (44e10914.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 70 (44e10918.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 71 (44e1091c.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 72 (44e10920.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 73 (44e10924.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 74 (44e10928.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 75 (44e1092c.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 76 (44e10930.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 77 (44e10934.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 78 (44e10938.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 79 (44e1093c.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 80 (44e10940.0): 4a100000.ethernet (GPIO UNCLAIMED) function cpsw_default group cpsw_default
pin 81 (44e10944.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 82 (44e10948.0): 4a101000.mdio (GPIO UNCLAIMED) function davinci_mdio_default group davinci_mdio_default
pin 83 (44e1094c.0): 4a101000.mdio (GPIO UNCLAIMED) function davinci_mdio_default group davinci_mdio_default
pin 84 (44e10950.0): 48030000.spi (GPIO UNCLAIMED) function spi0_pins group spi0_pins
pin 85 (44e10954.0): 48030000.spi (GPIO UNCLAIMED) function spi0_pins group spi0_pins
pin 86 (44e10958.0): 48030000.spi (GPIO UNCLAIMED) function spi0_pins group spi0_pins
pin 87 (44e1095c.0): 48030000.spi (GPIO UNCLAIMED) function spi0_pins group spi0_pins
pin 88 (44e10960.0): 481a6000.serial (GPIO UNCLAIMED) function pinmux_uart3_pins group pinmux_uart3_pins
pin 89 (44e10964.0): 481a6000.serial (GPIO UNCLAIMED) function pinmux_uart3_pins group pinmux_uart3_pins
pin 90 (44e10968.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 91 (44e1096c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 92 (44e10970.0): 44e09000.serial (GPIO UNCLAIMED) function pinmux_uart0_pins group pinmux_uart0_pins
pin 93 (44e10974.0): 44e09000.serial (GPIO UNCLAIMED) function pinmux_uart0_pins group pinmux_uart0_pins
pin 94 (44e10978.0): 48022000.serial (GPIO UNCLAIMED) function pinmux_uart1_pins group pinmux_uart1_pins
pin 95 (44e1097c.0): 48022000.serial (GPIO UNCLAIMED) function pinmux_uart1_pins group pinmux_uart1_pins
pin 96 (44e10980.0): 48022000.serial (GPIO UNCLAIMED) function pinmux_uart1_pins group pinmux_uart1_pins
pin 97 (44e10984.0): 48022000.serial (GPIO UNCLAIMED) function pinmux_uart1_pins group pinmux_uart1_pins
pin 98 (44e10988.0): 44e0b000.i2c (GPIO UNCLAIMED) function pinmux_i2c0_pins group pinmux_i2c0_pins
pin 99 (44e1098c.0): 44e0b000.i2c (GPIO UNCLAIMED) function pinmux_i2c0_pins group pinmux_i2c0_pins
pin 100 (44e10990.0): 48038000.mcasp (GPIO UNCLAIMED) function mcasp0_pins_sleep group mcasp0_pins_sleep
pin 101 (44e10994.0): 48038000.mcasp (GPIO UNCLAIMED) function mcasp0_pins_sleep group mcasp0_pins_sleep
pin 102 (44e10998.0): 48038000.mcasp (GPIO UNCLAIMED) function mcasp0_pins_sleep group mcasp0_pins_sleep
pin 103 (44e1099c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 104 (44e109a0.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 105 (44e109a4.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 106 (44e109a8.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 107 (44e109ac.0): 48038000.mcasp (GPIO UNCLAIMED) function mcasp0_pins_sleep group mcasp0_pins_sleep
pin 108 (44e109b0.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 109 (44e109b4.0): 44e10800.pinmux (GPIO UNCLAIMED) function pinmux_clkout2_pin group pinmux_clkout2_pin
pin 110 (44e109b8.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 111 (44e109bc.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 112 (44e109c0.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 113 (44e109c4.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 114 (44e109c8.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 115 (44e109cc.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 116 (44e109d0.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 117 (44e109d4.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 118 (44e109d8.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 119 (44e109dc.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 120 (44e109e0.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 121 (44e109e4.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 122 (44e109e8.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 123 (44e109ec.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 124 (44e109f0.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 125 (44e109f4.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 126 (44e109f8.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 127 (44e109fc.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 128 (44e10a00.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 129 (44e10a04.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 130 (44e10a08.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 131 (44e10a0c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 132 (44e10a10.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 133 (44e10a14.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 134 (44e10a18.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 135 (44e10a1c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 136 (44e10a20.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 137 (44e10a24.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 138 (44e10a28.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 139 (44e10a2c.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 140 (44e10a30.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 141 (44e10a34.0): (MUX UNCLAIMED) (GPIO UNCLAIMED)

0 Kemal R. Shakir over 8 years ago in reply to Ahn

TI__Guru 55345 points

Could you try to run your code with these pinmux rules and gpio exports.

&gpio1 {

pinctrl-names = "default";
pinctrl-0 = <&gpio1_pins>;

status = "okay";

cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
cd-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
cd-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;

};

&am33xx_pinmux {

gpio1_pins: gpio1_pins {
pinctrl-single,pins = <
0x78 ( PIN_INPUT | MUX_MODE7 ) /* (U18) gpmc_be1n.gpio1[28] */
0x80 ( PIN_INPUT | MUX_MODE7 ) /* (U9) gpmc_csn1.gpio1[30] */
0x84 ( PIN_INPUT | MUX_MODE7 ) /* (V9) gpmc_csn2.gpio1[31] */
>;
...............................................................................................................................
};

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am335x set gpio mode