Using same AM437x MDIO signals configuring PHY-1 for RGMII and PHY-2 for PRUICSS mode

Hi,

There is no image attached to your post. Please repost image.

Also please specify which software you are asking about.

The software which we are using is of AM437x Industrial Development Kit SDK.

Regards
B. Eshak

What's most important here is how you are going to combine the necessary RMII/MII pinmuxing for PHY2, seeing that you want to use in as RGMII on CPSW in one case, and MII on PRU in the other case. For RGMII on CPSW use case you must use the CPSW MDIO. For MII on PRU use case you must use the PRU MDIO. Do you intend to switch RGMII/MII on the fly? Most likely this will be impossible to do.

You can refer to the AM335X ICE Board Rev. 2.1 schematic: processors.wiki.ti.com/.../AM335x_Industrial_Communications_Engine_Board_Design_Files It demonstrates a CPSW MII/PRU MII switching solution.

Yes ,you are correct. we have connected AM4377 pins which supports both RGMII/MII signals.
Based on the user input (RGMII/PRU ICSS selection ) the software should take care with respect to mode settings for RGMII when configured for RGMII interface and mode settings for PRU MII signals when configured for PRU ICSS.

1. If you observe in the image, Option-1 ,Pins A17 and Pins B17 can be used as CPSW MDIO and PRU MDIO.
These pins are used as common MDIO signals for both PHY-1 and PHY-2.

If RGMII is required A17 and B17 can work as CPSW MDIO
If PRUICSS is required A17 and B17 can work as PRU MDIO.

Please clarify whether above mentioned can work hardware wise.

If yes, what modifications to be done in software wise to work functionally

2. For PHY-1 A17,B17 pins will be always work as CPSW MDIO

For PHY-2 , based on user selection (RGMII or PRUICSS ) , these pins need to be configured for PRU MDIO when PRU ICSS is selected.
In our requirement, User selection means when user selects for PRUICSS mode , the required PHY configuration settings need to stored and when the board reboots , PHY-2 should work in PRUICSS mode. Similarly for RGMII mode selection. Each time the board has to reboot for either of the mode to work.

Hope this clears .

3. Let us know whether our understanding is correct , for PHY-2 to work in RGMII only CPSW MDIO interface will work and PRU MDIO will not work. Similarly for PRUICSS only PRU MDIO interface will work and CPSW MDIO will not work.

I don't think you can use CPSW MDIO and PRU MDIO at the same time over the same pins. There is continuous traffic on these interfaces. I have asked the ISDK experts to comment further on this use case.

I understand that CPSW MDIO and PRU MDIO cannot be used at same time over same pins. Please confirm whether there is any time sharing can be provided in the software so that either CPSW MDIO or PRU MDIO can be effectively used over same pins.

Please provide any alternate solution with respect to the options(Option-1 and Option-2) which can meet our modes requirement.

Thanks

Regards

B. Eshak

Dear Gatchev

We have one clarification to make with respect to the AM335X ICE Board Rev. 2.1 schematic shared by you for reference.
In Schematic page No. 10, we have observed that CPSW MDIO and PRU MDIO signals are shorted as shown in below snapshot,

Which is same as combining the Option-1 and Option- 2 in our design.

1. Please confirm whether this hardware wise shorting both MDIO signals(CPSW and PRU) will be functional without any bus conflict.

2. Also let us know whether CPSW RMII/PRU MII has been tested and working fine in the AM335X ICE Board? If yes, please brief on how the software wise this switching between RMII/PRU MII is taken care, so that similarly we can do the modification in software for our design.

Request you to clarify our above queries.

Thank you

Regards

B. Eshak

Thanks Biser

Can you be little more brief on this implementation.
Our doubt is on using PRU MDIO for RGMII interface as well.

Since PRU MDIO is from PRU ICSS core and RGMII signals are from EMAC of the Processor.
So how the PRU MDIO signals can take control on RGMII interface.

Thanks

Regards
B. Eshak

Dear Biser/David

Thanks for the reply

Our software team will look in to the solution provided.

We want to check whether any solution available with respect to hardware.

As I have posted earlier with respect to shorting the MDIO lines, request you to look into this query.

I have pasted my query below again for your reference,

We have one clarification to make with respect to the AM335X ICE Board Rev. 2.1 schematic shared by you for reference.
In Schematic page No. 10, we have observed that CPSW MDIO and PRU MDIO signals are shorted as shown in below snapshot,

Which is same as combining the Option-1 and Option- 2 in our design.

1. Please confirm whether this hardware wise shorting both MDIO signals(CPSW and PRU) will be functional without any bus conflict.

2. Also let us know whether CPSW RMII/PRU MII has been tested and working fine in the AM335X ICE Board? If yes, please brief on how the software wise this switching between RMII/PRU MII is taken care, so that similarly we can do the modification in software for our design.

Request you to clarify our above queries.

Thank you

Regards

B. Eshak

Dear David

Thanks for the reply.

In AM335x ICE V2 design there are two PHY's

1. PHY1 supports PR1_MII0/RMII1

2. PHY2 supports PR1_MII1

Let us know whether PHY1 can be configured in RMII1 and PHY2 can be configured in PR1_MII1?

If yes, let us know how the MDIO lines are configured to support both the PHY1 in CPSW interface and PHY2 in ICSS interface.

Thank you

Regards

B. Eshak

Dear David

Looking forward for your reply.

Please clarify and confirm with respect to the concern about two PHY's connected to common MDIO signals (CPSW and/or PRU).

And PHY1 is working in RGMII/RMII mode and PHY2 is working in PR1_MII mode. How should MDIO signals should be configured and controlled so that PHY1 and PHY2 will work in different modes.

Thank you

Regards
B. Eshak