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When will UNDERRUN bit in PERI_TXCSR register of USB be set to 1?

morizzo
Intellectual 390 points

According to data sheet UNDERRUN bit is set to 1 when IN token is received with TXPKTRDY bit deasserted in isochronous transfer.

I want to know whether or not the UNDERRUN bit is set to 1 other than in isochronous transfer. 

Will this bit become 1 in bulk or interrupt transfer?

Thank you,

  • 0 in reply to Biser Gatchev-XID
    Intellectual 390 points
    I forgot it!

    I am going to use AM335x.

    Thanks,
  • 0 in reply to morizzo
    TI__Guru**** 393215 points
    I have asked the USB experts. Feedback will be posted directly here.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 390 points
    Thanks, Biser.

    I have an additional question on this.
    Will an interrupt also be generated when UNDERRUN is set to 1 ?

    In my application, AM335x is a USB device or a host and it must detect if IN token is issued by USB host in all kinds of USB transfer.

    Thanks,
  • 0
    TI__Guru*** 125366 points

    morizzo said:
    According to data sheet UNDERRUN bit is set to 1 when IN token is received with TXPKTRDY bit deasserted in isochronous transfer.

    I am not sure what datasheet you referred to, but the version I have does not mention UNDERRUN is for Isoch only. It is applicable for all transfer types.

    morizzo said:
    Will an interrupt also be generated when UNDERRUN is set to 1 ?

    Setting UNDERRUN bit itself does not generate interrupts. An interrupt is only generated when an IN token is received with all CSR bits set accordingly in this case, and your driver should check for UNDERRUN bit in the ISR.

  • 0 in reply to Bin Liu
    Intellectual 390 points

    Hello Bin,

    Thank you for your reply.

    I am not sure what datasheet you referred to, but the version I have does not mention UNDERRUN is for Isoch only. It is applicable for all transfer types.

    I read spruh73l.pdf. Isn't this a latest one?

    In the document UNDERRUN bit is explainged only in the section 16.3.8.1.4.1.3 "Isochronous IN Error Handling: Peripheral Mode." That is why I think it is available only in Iso transfer.

    How did you get to know "It is applicable for all transfer types." ? Let me know a source of the information if you have.

    Thank you,

  • 0 in reply to morizzo
    TI__Guru*** 125366 points

    morizzo said:
    I read spruh73l.pdf. Isn't this a latest one?

    Okay we typically call it TRM, so I didn't realize you meant this document.

    There is another document, which requires special NDA to share, describes the UNDERRUN bit as

    "The USB sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit."

    so it is not Isoch specific.

    The only reason I can think of why the UNDERRUN bit is mentioned in TRM only for Isoch transfers, is because UNDERRUN is a critical condition for Isoch transfers, but it is not for others, for example, Bulk transfers.

  • 0 in reply to Bin Liu
    Intellectual 390 points
    Thank you, Bin

    I verified that UNDERRUN bit is actually set to 1 when receiving an IN token using BeagleBone Black.
    Yes, you are correct. UNDERRUN bit is not isoch transfer specific.

    Again, thank you for your support.
  • 0 in reply to morizzo
    TI__Guru*** 125366 points

    Thanks for the update.