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AM3352 - U-boot - NAND BIT-FLIP CORRECTED.

RNJ
Prodigy 20 points

Hello everyone,


I'm passing for a trouble with my board with an AM3352BZCZD60 with one NAND SLC of Micron - MT29F1G08ABBDAH4-IT:D. We are facing NAND corrupted bytes on CRAMFS partition. Since this problem happened I'm looking for errors or mistakes that I could have made, after a review of all hardware parameters, power-up sequence, signal integrity, etc. I did not found anything strange on the hardware, so, to start looking in the software part I did one u-boot version that remapped all the device (excluding MLO and U-boot) and write in every sector of the nand one knowed sequence of data (ex: 0x55aa55aa...)

After that, I made the u-boot to read each single byte of the nand and compare with the previous information that I wrote and I expect to be there. This test is now passing for more than 70 hours of continuos operation and I have found 3 unexpected answers reporting on the u-boot console, similar to this : "reading address: 0x57a0000 to 0x589ffff | result: nand: bit-flip corrected @data=281".

Our nand is configured with BCH algorithm ECC.

I do not have idea if this could be the source of the CRAMFS corruption or if is acceptable a few nand-flip reports considering thousands of reading sequences, or worst, if this is another error that should not happen and there is no link between this and the CRAMFS corrupted in my kernel.


Is there anyone that already have passed for this? Any information or help is very welcome!


Thank you!

  • 0
    Genius 3685 points

    Cramfs is not suitable for NAND flash, because it does no wear leveling. NAND flashes need some sort of wear leveling even for R/O data.

    Use UBI/UBIFS.

  • 0 in reply to Wolfgang Muees1
    Prodigy 20 points
    Hello Wolfgang, thanks for your tip, but in fact I do not see why cramfs in the NAND could be the source of the problem, even Texas have tutorials showing how to do that, there is no exception or recommendation to avoid this file system in NAND.

    Could you share more information about that?

    And why wear leveling should be important considering read only data?
  • 0 in reply to RNJ
    Genius 3685 points

    And why wear leveling should be important considering read only data?


    Because NAND chips have a sort of failure that a read in sector A may cause a bit flip in sector B, with B in the neigbourhood of A.

    This sort of failure is present in newer chips (big capacity, MLC). Check the application notes of the NAND vendors.

    The recommendation of cramfs for NAND is outdated.

    regards

    Wolfgang