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AM571x PCIe Clocking

Nathan Rabenold
Intellectual 745 points

I am working on designing a PCIe interface between an AM571x processor and an FPGA.  In order to avoid an external oscillator on our board, I plan to use the ljcb_clk pins as outputs to provide the PCIe clock to our FPGA.

Looking at SPRUHZ7, AM571x Technical Reference Manual, Table 26-49 implies that only certain clock frequencies on the CLKINP input to the DPLL_PCIE_REF module are verified to meet PCIe clock jitter requirements.  This input is derived from SYS_CLK1, for which the datasheet states can be 19.2, 20, or 27MHz.  I had been planning on using a 20MHz system clock; however, this  is not listed in Table 26-49.  Is this configuration simply supported but not tested (assuming I set the multiplier/dividers accordingly to get the required 100MHz PCIe clock)?  Why do the frequency specifications of Table 26-49 not match the allowable options for system clock frequencies?

Thanks.

  • 0
    TI__Guru**** 393215 points
    Hi,

    Table 26-49 lists the combinations that have been verified to meet the PCIe clock jitter requirements. Other ratios combinations exist, to obtain a lower DCO frequency and lower power, but they should be checked against the PCIe standard.
  • 0 in reply to Biser Gatchev-XID
    Expert 1900 points

    Biser Gatchev-XID said:
    Table 26-49 lists the combinations that have been verified to meet the PCIe clock jitter requirements. Other ratios combinations exist, to obtain a lower DCO frequency and lower power, but they should be checked against the PCIe standard.

    Hi Biser, I have a follow-up question regarding this. Tables 26-49 and 26-50 show certain CLKINP values that can be used in either a "higher-power" or "lower-power" ratio configuration, both of which have been tested to meet PCIe jitter requirements.

    If low-power is not a significant concern for a design, then what would be the benefits of choosing to use a "higher-power" ratio configuration?

    Thanks for your help,
    Dave

  • 0 in reply to Butters
    TI__Guru*** 140115 points
    Dave

    Clock jitter and lock time are two differences between the low power and high power mode. For low power mode, you have to make sure jitter performance of the 100MHz clock meets the PCIe standard, and you also have to make sure the lock time meets your system requirement.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Expert 1900 points

    David, thank you for the response. Just to make sure that I understand -- is it safe to say that both clock jitter and lock time are improved (reduced) when operating in "high-power" mode? Thanks!

  • 0 in reply to Butters
    TI__Guru*** 140115 points
    Dave

    This is correct.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    TI__Guru*** 140115 points
    Dave

    Do you plan to use the PCIe interface in Gen1 2.5G or Gen2 5G mode?

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Expert 1900 points

    I would have liked to use Gen2 mode, but the latest AM571x datasheet revision (SPRS919K from earlier this month) indicates that only Gen1 mode is supported. A note in section 5.6.14 reads:

    The PCIe interfaces are compliant with the electrical parameters specified in PCI Express®
    Base Specification Revision 2.0. The data rate is limited to 2.5Gbps.

    Update: It seems that AM571x silicon revision 2.0 supports both Gen1 and Gen2; see SPRS957.

  • 0 in reply to David (ASIC) Liu
    TI__Mastermind 25296 points

    David,

    From this post I got what I wanted to confirm: the PCIe differential clock can be derived from internal, and can be output to external.

    2 more questions hope get your confirmation:

    #1. About the Jitter performance, does it depends on jitter of clock source CLKIN? will the Jitter changed after PLL ? or even after PLL multiplication, Jitter is same as ClKIN?

    X15 board use 20MHz CLKIN, but this frequency is not listed in Table 26-49, is it due the oscillator on the board doesn't meet Jitter requirement, failed on verification so not listed it? otherwise it doesn't make sense TI official board with 20MHz CLKIN, but the board list other frequency excluded 20MHz.

    #2. What is mean of lower-power ratio and higher-power ratio? does it depends on DCO clock frequency? what is the frequency to determine it?