This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5728 VOUT1 Issue

Other Parts Discussed in Thread: AM5728

Hi All,

We have been trying to test 1080p60 display on VOUT1 interface of AM5728. We are using the following setup.

 AM5728 VOUT1 Port --> SDI Transmitter --> SDI Cable --> SDI Receiver

 We see data corruption at the SDI receiver and it is detecting it as invalid standard. On debugging further we found out that the jitter present on the VOUT1 clock is too high.

It is around 600 picoseconds which is 2UI (User Intervals) for the 1080p60 data rate of 3Gbps. The SDI transmitter IC is thus not able to remove this jitter and hence the output is not proper.

Please find attached the jitter measurement. We have used the manual mode delay values for VOUT1 pins and are giving data at the positive edge of the clock.

 

Can you please help us out in finding the root cause and resolving the same.

Regards

Ayusman

  • Hi,

    I will forward this to the Video experts. Please note that reply may be delayed due to upcoming holidays.
  • ayusman mohanty1 said:

    On debugging further we found out that the jitter present on the VOUT1 clock is too high.

    It is around 600 picoseconds

    How did you determine that the 600ps jitter was the issue?  Does the device you're connecting to have an explicit jitter requirement?  It seems more likely to me that you're marginal on either the setup or hold time.  What device are you connecting to?

  • Hi Brad,

    We have measured the same on a CRO using persistence mode.

    To give you an idea,we have a AM572x based processor board which when we connect to another board where the SDI transmitter is present. We are using a Semtech SDI transmitter on board . On checking with Semtech FAE , we came to know that this is because the input clock to the transmitter has jitter, more than what the transmitter can work with. We see this issue only with 1080p60 where line rate is 3Gbps. For 3Gbps, the clock period is 300ps, and the clock jitter is coming to 2UI. This is causing bit errors.

    We dont doubt the SDI transmitter as we also have tested the same board with DM816x based processor board and it works fine.

    Can you share with us, what is the jitter in the video port clock which you have measured as a part of your testing.
    Do let us know, how we can proceed further on this.


    regards
    Ayusman
  • Hi Brad,

    Did you get a chance to go through my reply. We need to close this as early as possible, as we are not able to use the boards.

    Regards
    Ayusman
  • You never answered my question. What is the jitter requirement? I assume there's some kind of PLL in the external device for the SERDES. What is the clock source for it? Is it using the pixel clock as the clock source to the SERDES PLL? I think you need to have a broader look at all your clocking, e.g. how are you clocking the display output, the external chip, etc.? I expect the reason it worked on the DM816x relates to something different you did with clocking at the board level (e.g. lower PPM crystal, etc.).
  • Hi Brad,

    Sorry, If I was not clear in my answer. As such there is no specific requirement of jitter. Our aim is to interface the AM5728 with the SDI transmitter. Yes, there is a SERDES PLL in the transmitter and the clock source for it is the video clock from the AM5728. Since the clock from AM5728 is not proper, the output of transmitter is also not proper.

    Also, to help you understand better, we have the SDI transmitter on a daughter board and we have two processor boards (one with AM5728, other with DM816x). With the same daughter board when I connect the AM5728 board, it doesnot work. Whereas if I replace it with the DM816x board then it works. This is why we were wondering what exactly is the difference in AM5728 and DM816x that it works with one and not with the other.

    Hope this clarifies. Can you please help us out in finding out the root cause.

    Regards
    Ayusman
  • ayusman mohanty1 said:
    Yes, there is a SERDES PLL in the transmitter and the clock source for it is the video clock from the AM5728. Since the clock from AM5728 is not proper, the output of transmitter is also not proper.

    Along these same lines, the input clock to the AM5728 is going to impact the jitter on the outputs of the AM5728.

    ayusman mohanty1 said:
    With the same daughter board when I connect the AM5728 board, it doesnot work. Whereas if I replace it with the DM816x board then it works.

    How does the jitter of the input clock compare across these two boards?

    Also, please have a look in the TRM at Section 11.1.2.1 "Display Subsystem Clocks".  As you can see there are multiple options for clocking the display subsystem. Can you please provide some details on how you have the muxes/PLLs configured?

  • Hi Brad,

    We have used ABM7-20.000MHZ-D2Y-T on AM5728 board.
    This is the same crystal used on AM57xx EVM.
    The same family of crystal is also used on the DM816x board with a different frequency of 27MHz.
    Both of them have the same specifications.

    I will share with you the PLL configurations.

    Regards
    Ayusman
  • Hi Brad,

    Please find the details below:
    1. The functional clock to Display Controller (F_CLK) is sourced from DSS_CLK which in turn is sourced from CLKOUTX2_H12 of DPLL_PER.
    2. The interface clock to VOUT1 (LCD1_CLK) is sourced from DPLL_DSI1_A_CLK1 which is sourced from DPLL_VIDEO1 PLL.

    CLKOUTX2_H12 is generated from SYSCLK1.
    The frequency of CLKOUTX2_H12 is 153.6 MHz with multiplier and divider values as follows: M = 96, N+1=5, M5_H12+1=5.

    DPLL_VIDEO1 is directly generated from SYSCLK1.
    The frequency of DPLL_DSI1_A_CLK1 is 148.5 MHz with multiplier and divider values as follows: M=594, N+1=8, M4+1=10.

    Do let us know, how we can proceed with this. It is important for us to find the root cause.

    Regards
    Ayusman
  • ayusman mohanty1 said:
    DPLL_VIDEO1 is directly generated from SYSCLK1.
    The frequency of DPLL_DSI1_A_CLK1 is 148.5 MHz with multiplier and divider values as follows: M=594, N+1=8, M4+1=10.

    PLL jitter is minimized by keeping N as small as possible.  For starters please try M=297, N+1=4, M4+1=10.

  • Dear Brad,

    We tried out with this, but still the issue persists. Any other idea you have which we can try out?

    regards
    Ayusman
  • What jitter was measured in that scenario? Was it improved, i.e. was that a step in the right direction?

  • We got same value of jitter and there was no improvement. Any thing else is there which we can try it out.

  • If you want to improve jitter substantially, then you need to change the internal clock source entirely. DPLL_VIDEO1 is a type A DPLL. The type B DPLL's have better jitter characteristics. So instead of clocking with DPLL_VIDEO1 you should instead be using DPLL_HDMI. The main mux you need to pay attention to is controlled inside CTRL_CORE_DSS_PLL_CONTROL. In your particular case where you're trying to configure LCD1_CLK, we want to look at bits 4:3 DSI1_A_CLK1_SELECTION. Currently those bits are configured to 0x0 (DPLL_VIDEO1), but you'll want to switch that to 0x1 (DPLL_HDMI) and correspondingly configure DPLL_HDMI.
  • Dear Brad,

    We tried to change the N parameter as suggested by you. However we didnot see any improvement.

    Also you had asked to change the PLL to DPLL_HDMI. On going through the code we realized it is not that straight forward and will need a good amount of effort to change. Do you have tried using DPLL_HDMI with VOUT interfaces. If so, can you please share the patch with us so that we can try it out.

    Regards
    Ayusman
  • Ayusman,

    I checked with the Linux team and it sounded like it would be a major effort to use DPLL_HDMI.  However, after spending more time reviewing the PLL numbers, I think we can actually do much better in terms of jitter.  Besides wanting to minimize N, you also want to maximize M.  There's a bit of a balance here.  The value of N will determine the refclk of the DPLL.  Generally speaking you should aim to keep it greater than or equal to 1 MHz.  You want to make M as large as possible, but you need to make sure the output clock (DCOCLK) stays within the DPLL spec of 2800 MHz.

    That said, I think this should be a major improvement over the previous numbers:

    DPLL_VIDEO config (N=14, M=891, M4=15)

    • refclk = 20 MHz / (14+1) = 1.333 MHz
    • DCOCLK = 1.333 MHz x 891 x 2 = 2376 MHz
    • clkout1 = 2376 MHz / (15+1) = 148.5 MHz

    Brad

  • Actually, hang on a minute...  One of my colleagues pointed out an errata specifically related to this issue.  Please look for i886 in the AM572x errata.  I've been sending you down the direction of "the usual way DPLLs work", but there's an errata here so that is going to supersede the usual way...

    Along the lines of "option B" from the errata guidelines, the recommended values for you to use are:

    Option B modified for faster output (N=119, M=1782, M4=3)

    • refclk = 20 MHz / (119+1) = 0.16667 MHz
    • DCOCLK = 0.16667 MHz x 1782 x 2 = 594 MHz
    • clkout1 = 594 MHz / (3+1) = 148.5 MHz

    Read through the errata i886 description.  It's the exact same issue you're having.  I wish one of us had checked sooner!

  • Dear Brad,

    We actually did come across this Errata and tried with the values but they didnot work out.

    Please find below the values, we have tried so far and the corresponding observations.

    Sl.No M N M4 148.5M 74.25
    1 297 7 9 No Yes
    2 1782 7 9 No No
    3 1782 119 3 No No
    4 594 7 9 No Yes

    I have not tried out the combination of (891/14/15). 

    My default combination was 594/7/9 where the 74.25MHz clock was working properly. But with the changes suggested by you, that also stopped working. Any ideas on how the jitter deteriorated.

    Regards

    Ayusman

  • What are the PLL settings that you used successfully on the DM816x?

  • Can we connect Vout directly to the serializer IC Please specify the LCD output port format supported by AM5728